Pons-Escat, Lucía; Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Petit Martí, Salvador Vicente; Pons Terol, Julio; Huang, Chaoyi(Elsevier, 2023-01)
[EN] The increasing popularity of cloud computing has forced cloud providers to build economies of scale to meet the growing demand. Nowadays, data-centers include thousands of physical machines, each hosting many virtual ...
Lorente Garcés, Vicente Jesús; Valero Bresó, Alejandro; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Canal, Ramón; López Rodríguez, Pedro Juan; Duato Marín, José Francisco(IEEE, ACM, 2013-03-18)
Low-power modes in modern microprocessors rely
on low frequencies and low voltages to reduce the energy budget.
Nevertheless, manufacturing induced parameter variations can
make SRAM cells unreliable producing hard ...
Valero Bresó, Alejandro; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; López Rodríguez, Pedro Juan; Duato Marín, José Francisco(Association for Computing Machinery (ACM), 2012)
Memory latency has become an important performance bottleneck in current microprocessors. This problem aggravates as the number of cores sharing the same memory controller increases. To palliate this problem, a common ...
Feliu Pérez, Josué(Universitat Politècnica de València, 2017-03-27)
The recent multicore era and the incoming manycore/manythread era generate a lot of challenges for computer scientists going from productive parallel programming, over network congestion avoidance and intelligent power ...
Pons Escat, Lucía; Selfa Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Pons Terol, Julio(Universitat Politècnica de València, 2020-05-14)
CPA is LLC (Last Level Cache) partitioning approach that performs an efficient cache space distribution among executing applications. To assign partitions (ways) of the LLC, Intel CAT is used. This policy is included in a ...
Lurbe Sempere, Manel(Universitat Politècnica de València, 2020-09-28)
[ES] Los procesadores de altas prestaciones más modernos integran prefetchers hardware muy complejos, en los que seleccionar la configuración para que éste obtenga las mejores prestaciones se convierte en una tarea compleja. ...
Lurbe-Sempere, Manel; Feliu-Pérez, Josué; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio(Institute of Electrical and Electronics Engineers, 2022-10-01)
[EN] Current multi-core processors implement sophisticated hardware prefetchers, that can be configured by application (PID),to improve the system performance. When running multiple applications, each application can present ...
Valero Bresó, Alejandro; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; López Rodríguez, Pedro Juan; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2015-07)
In recent years, embedded dynamic random-access memory (eDRAM) technology has been implemented in last-level
caches due to its low leakage energy consumption and high density. However, the fact that eDRAM presents slower ...
Valero Bresó, Alejandro; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; López Rodríguez, Pedro Juan; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2012-09)
SRAM and DRAM have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not ...
Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente(Elsevier, 2018)
[EN] Computer architecture courses typically include lab sessions to reinforce, from a practical perspective, concepts and architectural mechanisms studied in lectures. Lab sessions are mainly based on simulation frameworks ...
Yuste Romero, David(Universitat Politècnica de València, 2011-11-17)
Desarrollo de una técnica para la paralelización automática de código secuencial basada en la ejecución concurrente de llamadas a función independientes. También forma parte de esta tesina la implementación de dicha técnica ...
Navarro Alfonso, Paula(Universitat Politècnica de València, 2013-09-30)
El objetivo de este trabajo es diseñar técnicas eficientes aplicables al controlador
de memoria para reducir este tiempo de acceso. Asumiremos que el sistema
base ya implementa técnicas de prebúsqueda, que es una técnica ...
Bautista Rayo, Diana(Universitat Politècnica de València, 2011-11-17)
En este trabajo se presentan dos planificadores con reducción energética para la planificación de tareas de tiempo real basándose en procesadores multicore multihilo de grano
grueso. Ambos planificadores implementan las ...
March Cabrelles, José Luis(Editorial Universitat Politècnica de València, 2015-03-30)
The continuous shrink of transistor sizes has allowed more complex and powerful devices
to be implemented in the same area, which provides new capabilities and functionalities.
However, this complexity increase comes ...
Pons-Escat, Lucía; Feliu-Pérez, Josué; Puche-Lara, José; Huang, Chaoyi; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio(Elsevier, 2022-06)
[EN] Multithreaded latency-critical applications represent an important subset of workloads running on public cloud systems. Most of these systems deploy powerful computing servers including Intel Hyper-Threading processors. ...
Petit Martí, Salvador Vicente(Universitat Politècnica de València, 2008-07-31)
En la presente tesis se realiza una evaluación exhaustiva de ls Sistemas de Memoria Distribuida conocidos como Sistemas de Memoria Virtual Compartida. Este tipo de sistemas posee características que los hacen especialmente ...
Candel Margaix, Francisco(Universitat Politècnica de València, 2019-09-02)
[ES] En los últimos años, la creciente necesidad de la capacidad de cómputo ha supuesto un reto que ha llevado a la industria a buscar arquitecturas alternativas a los procesadores superescalares con ejecución fuera de ...
Candel-Margaix, Francisco; Valero Bresó, Alejandro; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio(Institute of Electrical and Electronics Engineers, 2019-10-01)
[EN] To support the massive amount of memory accesses that GPGPU applications generate, GPU memory hierarchies are becoming more and more complex, and the Last Level Cache (LLC) size considerably increases each GPU generation. ...