In this thesis we have designed several hardware architectures of some typical digital subsystems for high performance communications systems, aiming at optimized implementations for these systems. The work has focused on two areas: the approximation of elementary functions, specifically the logarithm and arctangent, and the design of an emulator of additive Gaussian noise channel. The architectures have been designed at all times with the objective to achieve an efficient implementation in Field Programmable Gate Arrays devices (FPGAs), due to its increasing use in digital high performance communications systems. For the approximation of logarithm we have proposed two different architectures, one based on the use of multipartite table methods and the other based on the Mitchell’s approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that corrects the piecewise interpolation error. A first architecture for the approximation of atan(y/x) is based on the computation of the reciprocal of x and the arctangent approximation, using multipartite Look-up tables (LUTs). This proposal reduces the power consumption compared to the best techniques described in the literature, such based on CORDIC. A second strategy for the approximation of atan(y/x) is based on logarithmic transformations, which transforms the calculation of the division of two inputs in a simple subtraction and requires the computation of atan(2w). This second strategy has resulted in two architectures, a first in which both the logarithm and atan(2w) have been implemented using multipartite LUTs, also combined with the use of non-uniform segmentation techniques in the calculation of atan(2w), and a second architecture using a piecewise linear interpolation with power-of-two slopes and correction tables. The results obtained with this strategy improve the first architecture discussed. Two architectures for the approximation of arctangent and one for the logarithm have resulted in three publications in internationals journals. We also have proposed several architectures for a Gaussian white noise generator. The designs are based on the Inversion method, specifically approximating the inverse of cumulative distributions functions by polynomial interpolation and non-uniform segmentation. These architectures offer its output a standard deviation of ±13.1σ and 13 fractional bits, higher values than practically all hardware generators present in the literature, employing, in comparison, fewer FPGA resources. Compared to Gaussian channel implementations based on the inversion method presented by other authors, our architectures achieve a significant reduction in area partially or completely eliminating the barrel-shifter. The results for Gaussian channel emulator have been sent to an international journal, being currently under review process.