Abstract 
Multi-core designs are becoming a more and more popular solution to most of the single-core designs limitations. A multi-core design follows the System on-Chip (SoC) paradigm, in which several cores are integrated into a single chip. The performance of SoC designs is heavily influenced by the interconnection infrastructure implemented: while small SoCs designs can employ buses as their interconnection, more complex interconnections are required as the number of cores of the design increases. 
In this context, the Network on-Chip (NoC) paradigm arises as a solution to the interconnection challenges of new SoC designs. In a NoC, transactions between cores are encapsulated into packets, and delivered through a shared interconnection network. This concept is adopted from the off-chip interconnection networks field, and thus it can inherit most of the techniques of this mature field. Anyway, the on-chip environment presents different constraints than the off-chip one. For example, buffer size is a critical design parameter for any on-chip design, while it is a more relaxed constraint in off-chip ones. For this reason, techniques from the off-chip domain should not be taken for granted when implementing a NoC, but revised and adapted by taking into account the special characteristics of the on-chip domain. 
   In particular, in the on-chip domain the relentless pace of technology scaling to the nanoscale regime is bringing physical effects into the forefront. For this reason, visibility of the lower layers of the design hierarchy is required to accurately assess the capabilities of any given NoC design. In SoCs, the on-chip interconnect will be implicated in every communication stream. Therefore, the NoC physical characteristics are critical for overall SoC performance. In this context, SoC designs will be viable only when taking silicon aware decision at each layer of the design hierarchy. However, this does not affect to need for fast design space exploration frameworks by means of abstract tools, hence making the accuracy-exploration speed trade-off increasingly difficult to cope with. For a given design space, the high heterogeneity (architectural and technological) of NoC solutions increases the complexity of selecting the optimal NoC configuration. A common approach is to use high level tools to provide performance estimations that the designer will use to select the most promising candidates at the earlier stages of the design flow. But there is a gap between the performance predictions of high-level tools and the real performance achieved after the system is implemented. In fact, this gap is growing, as the number of libraries available for a given technology node increases, forcing to increase the number of design re-spins due to inaccurate high level predictions, which results in increased design cost. The ultimate implication is that back-annotations from the lower layers of the design hierarchy need to be exposed to design tools operating at the upper layers, finding a new trade-off between simulation and/or exploration speed and layout awareness. Current front-end tools for use in the early design stages suffer from performance mispredictions, since they often ignore the technology platform. The challenge in finding the new trade-off point is that when considering both front-end and back-end issues (e.g., multiple technology libraries, core size), the design space becomes even wider than it is now. 
   This dissertation focuses on the development of a new set of front-end design, modeling and simulation tools for layout-aware pruning of the design space toward the most promising candidates. As an outcome of this dissertation, NoC designers will be able to take advantage of a new set of design space exploration tools reducing time-to-market and bridging the accuracy gap with the lower layers of the design process. In a first step, we focused on the design and development of an experimental setting for use in the analysis of alternative architecture design techniques. Since the objective is the analysis of a large range of implementation alternatives, it was decided to pursue transaction-level simulations. Hence, the dissertation reports on an extensive abstraction and modeling effort of NoC architecture building blocks while retaining accuracy of functionally equivalent Register Transfer Level (RTL) models. As a result, dramatic improvements in simulation speed were achieved. At the same time, all abstract models were parameterized with some key parameters from the physical synthesis (e.g., target frequency, link latency), thus being able to evaluate points in the design space quickly and with high accuracy. 
   In the second step, by using the developed abstract simulation framework layout awareness was brought to the upper layers of NoC design, by reviewing architectural design techniques mutated from the off-chip domain in light of layout constraints, selecting the most promising candidates and in some cases even exploiting the distinctive features of the on-chip setting to come up with radically new (and even counterintuitive) solutions. This activity, which was preliminary to the design of the Design Space Exploration (DSE) tool, was aimed at gaining that layout awareness that the tool itself should have. The activity was split into two stages. 
   On one hand, starting from a theoretical description of the most popular topologies proposed for NoCs in the open literature, the developed simulation framework was employed in order to demonstrate and address the above mentioned gap. Concrete examples of the abstraction and accuracy gap will be provided for industry-relevant NoC configurations and the methodology will be put at work to close this gap, hence coming up with trustworthy cross-benchmarking indications. To demonstrate the potentials of the new NoC investigation framework, the topology analysis process will be extended to a number of architecture variants, featuring different size, floor planning constraints, technologies and even HW/SW interaction patterns. Additionally, the most common pitfalls of topology physical design will be highlighted, and most common techniques to address them will be analyzed both in terms of achieved performance and cost overhead. 
   On the other hand, during the research on the topology exploration topic, several topologies were considered that require the use of the virtual channels flow control mechanism in order to reach their maximum potential. This very popular technique has been used for several years in off-chip networks for a broad number of reasons, and thus, its use has been widely advocated for NoCs. The most common VC architecture for NoCs proposed in the open literature is mutated from off-chip networks. Although fully functional in the NoC context, this architecture is aimed to a different environment and results in an overly large area and delay overhead. For this reason, we propose and evaluate an implementation of VC better suited for the constraints of NoCs and therefore able to provide a considerable improvement both in performance and in area/power over the commonly proposed implementation, with the aim of demonstrating the mismatch between smart architecture design techniques conceived for off-chip interconnection networks and an on-chip setting. 
   Finally, we focused on the development of the Design Space Exploration (DSE) tool. Our approach to this challenge is two-folded. On one hand, we capitalize the knowledge gained in previous steps on silicon-aware architecture design choices and simulation tools, to build a CAD tool to aid in the design of NoC-based systems. On the other hand, we introduce some techniques to reduce the time-to-market of new designs via DSE acceleration and fast re-spin techniques.