The high level of computing power required for some applications can only be achieved by multiprocessor systems. These systems consist of several processors that communicate by means of an interconnection network. The huge increase both in size and complexity of high-end multiprocessor systems has triggered up their power consumption. Power consumption reduction techniques are being applied everywhere in computer systems and the interconnection network must not be an exception. 

In this scenario, the most widely used interconnection networks are based on regular topologies: direct topologies, as torus, and indirect topologies, as fat-tree. In both cases the power consumed by the interconnect circuitry has a non-negligible contribution to the total system budget. 

In this thesis, we propose a strategy to reduce interconnection network, based both on direct and indirect topologies, power consumption. The strategy is implemented by means of a mechanism that combines two alternative techniques: (i) dynamically switching on and off network links as a function of traffic (any link can be switched off, provided that network connectivity is guaranteed), (ii) dynamically setting the available link bandwidth as a function of traffic. In both cases, the topology of the network is not modified. Therefore, the same routing algorithm can be used regardless of the power saving actions taken, thus simplifying router design.

Our results show that the network power consumption can be greatly reduced, at the expense of some increase in latency. However, the achieved power reduction is always higher than the latency penalty.