library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divisor1 is

Port ( CLK : in STD_LOGIC;
		 RST : in STD_LOGIC;
		 salida : out STD_LOGIC);
end divisor1;

architecture Behavioral of divisor1 is
signal Qint: STD_LOGIC_VECTOR (10 downto 0);
signal sint: STD_LOGIC;

begin

process (CLK, RST)
begin
	if RST = '1' then Qint <= "00000000000"; sint <= '0';
	elsif (CLK' event) and (CLK = '1') then
		if Qint = 1041 then
		Qint <= "00000000000"; sint <= '1';
		else Qint <= Qint+1; sint <= '0';
		end if;
	end if;
end process;

salida <= sint;

end Behavioral;

