library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DMUX is
    Port ( 	CLK : in  STD_LOGIC;                                    -- Tiene que funcionar a 48000 * 21
				Qint : in STD_LOGIC_VECTOR (4 downto 0);
				sen : in integer;
				Bf : out STD_LOGIC_VECTOR (7 downto 0);
				B1 : out STD_LOGIC_VECTOR (7 downto 0);
				B2 : out STD_LOGIC_VECTOR (7 downto 0);
				B3 : out STD_LOGIC_VECTOR (7 downto 0);
				B4 : out STD_LOGIC_VECTOR (7 downto 0);
				B5 : out STD_LOGIC_VECTOR (7 downto 0);
				B6 : out STD_LOGIC_VECTOR (7 downto 0);
				B7 : out STD_LOGIC_VECTOR (7 downto 0);
				B8 : out STD_LOGIC_VECTOR (7 downto 0);
				B9 : out STD_LOGIC_VECTOR (7 downto 0);
				B10 : out STD_LOGIC_VECTOR (7 downto 0);
				B11 : out STD_LOGIC_VECTOR (7 downto 0);
				B12 : out STD_LOGIC_VECTOR (7 downto 0);
				B13 : out STD_LOGIC_VECTOR (7 downto 0);
				B14 : out STD_LOGIC_VECTOR (7 downto 0);
				B15 : out STD_LOGIC_VECTOR (7 downto 0);
				B16 : out STD_LOGIC_VECTOR (7 downto 0);
				B17 : out STD_LOGIC_VECTOR (7 downto 0);
				B18 : out STD_LOGIC_VECTOR (7 downto 0);
				B19 : out STD_LOGIC_VECTOR (7 downto 0)
				);
end DMUX;

architecture Behavioral of DMUX is

signal Bf_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B1_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B2_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B3_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B4_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B5_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B6_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B7_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B8_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B9_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B10_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B11_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B12_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B13_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B14_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B15_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B16_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B17_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B18_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal B19_5 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');

begin

Process (CLK)																							-- Se mantenga dato durante un ciclo							
	begin	
		if (CLK'event and CLK='1') then															
			if (Qint="00001") then Bf_5 <= conv_std_logic_vector(sen,8);      		-- para que funcione Qint ="00001"
			elsif (Qint="00010") then B1_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="00011") then B2_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="00100") then B3_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="00101") then B4_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="00110") then B5_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="00111") then B6_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01000") then B7_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01001") then B8_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01010") then B9_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01011") then B10_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01100") then B11_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01101") then B12_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01110") then B13_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="01111") then B14_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="10000") then B15_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="10001") then B16_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="10010") then B17_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="10011") then B18_5 <= conv_std_logic_vector(sen,8);
			elsif (Qint="10100") then B19_5 <= conv_std_logic_vector(sen,8);
			end if;			
		end if;
end process;	
		
Bf <= Bf_5;
B1 <= B1_5;
B2 <= B2_5;
B3 <= B3_5;
B4 <= B4_5;
B5 <= B5_5;
B6 <= B6_5;
B7 <= B7_5;
B8 <= B8_5;
B9 <= B9_5;
B10 <= B10_5;
B11 <= B11_5;
B12 <= B12_5;
B13 <= B13_5;
B14 <= B14_5;
B15 <= B15_5;
B16 <= B16_5;
B17 <= B17_5;
B18 <= B18_5;
B19 <= B19_5;
		
end Behavioral;

