library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sumfas is
    Port ( 	fase1 : in STD_LOGIC_VECTOR (8 downto 0);
				fase2 : in STD_LOGIC_VECTOR (8 downto 0);
				fase3 : in STD_LOGIC_VECTOR (8 downto 0);
				fase4 : in STD_LOGIC_VECTOR (8 downto 0);
				fase5 : in STD_LOGIC_VECTOR (8 downto 0);
				fase6 : in STD_LOGIC_VECTOR (8 downto 0);
				fase7 : in STD_LOGIC_VECTOR (8 downto 0);
				fase8 : in STD_LOGIC_VECTOR (8 downto 0);
				fase9 : in STD_LOGIC_VECTOR (8 downto 0);
				fase10 : in STD_LOGIC_VECTOR (8 downto 0);
				fase11 : in STD_LOGIC_VECTOR (8 downto 0);
				fase12 : in STD_LOGIC_VECTOR (8 downto 0);
				fase13 : in STD_LOGIC_VECTOR (8 downto 0);
				fase14 : in STD_LOGIC_VECTOR (8 downto 0);
				fase15 : in STD_LOGIC_VECTOR (8 downto 0);
				fase16 : in STD_LOGIC_VECTOR (8 downto 0);
				fase17 : in STD_LOGIC_VECTOR (8 downto 0);
				fase18 : in STD_LOGIC_VECTOR (8 downto 0);
				fase19 : in STD_LOGIC_VECTOR (8 downto 0);
				Bf_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B1_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B2_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B3_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B4_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B5_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B6_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B7_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B8_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B9_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B10_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B11_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B12_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B13_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B14_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B15_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B16_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B17_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B18_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B19_2 : in STD_LOGIC_VECTOR (19 downto 0);	
				Bf_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B1_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B2_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B3_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B4_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B5_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B6_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B7_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B8_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B9_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B10_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B11_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B12_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B13_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B14_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B15_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B16_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B17_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B18_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B19_3 : out STD_LOGIC_VECTOR (8 downto 0)
				);
end sumfas;

architecture Behavioral of sumfas is

begin

				Bf_3 <= Bf_2(19 downto 11);
				B1_3 <= B1_2(19 downto 11) +  fase1;
				B2_3 <= B2_2(19 downto 11) +  fase2;
				B3_3 <= B3_2(19 downto 11) +  fase3;
				B4_3 <= B4_2(19 downto 11) +  fase4;
				B5_3 <= B5_2(19 downto 11) +  fase5;
				B6_3 <= B6_2(19 downto 11) +  fase6;
				B7_3 <= B7_2(19 downto 11) +  fase7;
				B8_3 <= B8_2(19 downto 11) +  fase8;
				B9_3 <= B9_2(19 downto 11) +  fase9;
				B10_3 <= B10_2(19 downto 11) +  fase10;
				B11_3 <= B11_2(19 downto 11) +  fase11;
				B12_3 <= B12_2(19 downto 11) +  fase12;
				B13_3 <= B13_2(19 downto 11) +  fase13;
				B14_3 <= B14_2(19 downto 11) +  fase14;
				B15_3 <= B15_2(19 downto 11) +  fase15;
				B16_3 <= B16_2(19 downto 11) +  fase16;
				B17_3 <= B17_2(19 downto 11) +  fase17;
				B18_3 <= B18_2(19 downto 11) +  fase18;
				B19_3 <= B19_2(19 downto 11) +  fase19;

end Behavioral;

