library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FF1 is
    Port ( 	CLK : in  STD_LOGIC;                                    -- Tiene que funcionar a 48000
				Bf_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B1_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B2_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B3_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B4_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B5_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B6_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B7_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B8_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B9_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B10_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B11_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B12_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B13_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B14_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B15_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B16_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B17_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B18_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B19_3 : in STD_LOGIC_VECTOR (8 downto 0);
				Bf : out STD_LOGIC_VECTOR (8 downto 0);
				B1 : out STD_LOGIC_VECTOR (8 downto 0);
				B2 : out STD_LOGIC_VECTOR (8 downto 0);
				B3 : out STD_LOGIC_VECTOR (8 downto 0);
				B4 : out STD_LOGIC_VECTOR (8 downto 0);
				B5 : out STD_LOGIC_VECTOR (8 downto 0);
				B6 : out STD_LOGIC_VECTOR (8 downto 0);
				B7 : out STD_LOGIC_VECTOR (8 downto 0);
				B8 : out STD_LOGIC_VECTOR (8 downto 0);
				B9 : out STD_LOGIC_VECTOR (8 downto 0);
				B10 : out STD_LOGIC_VECTOR (8 downto 0);
				B11 : out STD_LOGIC_VECTOR (8 downto 0);
				B12 : out STD_LOGIC_VECTOR (8 downto 0);
				B13 : out STD_LOGIC_VECTOR (8 downto 0);
				B14 : out STD_LOGIC_VECTOR (8 downto 0);
				B15 : out STD_LOGIC_VECTOR (8 downto 0);
				B16 : out STD_LOGIC_VECTOR (8 downto 0);
				B17 : out STD_LOGIC_VECTOR (8 downto 0);
				B18 : out STD_LOGIC_VECTOR (8 downto 0);
				B19 : out STD_LOGIC_VECTOR (8 downto 0)
				);
end FF1;

architecture Behavioral of FF1 is

signal Ff : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F1 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F2 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F3 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F4 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F5 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F6 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F7 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F8 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F9 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F10 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F11 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F12 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F13 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F14 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F15 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F16 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F17 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F18 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');
signal F19 : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');

begin

Process (CLK)										
	begin	
		if (CLK'event and CLK='1') then				
			Ff <= Bf_3;
			F1 <= B1_3;
			F2 <= B2_3;
			F3 <= B3_3;
			F4 <= B4_3;
			F5 <= B5_3;
			F6 <= B6_3;
			F7 <= B7_3;
			F8 <= B8_3;
			F9 <= B9_3;
			F10 <= B10_3;
			F11 <= B11_3;
			F12 <= B12_3;
			F13 <= B13_3;
			F14 <= B14_3;
			F15 <= B15_3;
			F16 <= B16_3;
			F17 <= B17_3;
			F18 <= B18_3;
			F19 <= B19_3;
		end if;
end process;

Bf <= Ff;
B1 <= F1;
B2 <= F2;
B3 <= F3;
B4 <= F4;
B5 <= F5;
B6 <= F6;
B7 <= F7;
B8 <= F8;
B9 <= F9;
B10 <= F10;
B11 <= F11;
B12 <= F12;
B13 <= F13;
B14 <= F14;
B15 <= F15;
B16 <= F16;
B17 <= F17;
B18 <= F18;
B19 <= F19;

end Behavioral;

