library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity arm is
    Port ( 	CLK : in  STD_LOGIC;                                    -- Tiene que funcionar a 48000
				num_nota : in STD_LOGIC_VECTOR (4 downto 0);  
				num_inst : in STD_LOGIC_VECTOR (1 downto 0);
				RST : in STD_LOGIC;
				INCe : in integer;
				INC : in STD_LOGIC_VECTOR (17 downto 0);
				Bf : out STD_LOGIC_VECTOR (19 downto 0);
				B1 : out STD_LOGIC_VECTOR (19 downto 0);
				B2 : out STD_LOGIC_VECTOR (19 downto 0);
				B3 : out STD_LOGIC_VECTOR (19 downto 0);
				B4 : out STD_LOGIC_VECTOR (19 downto 0);
				B5 : out STD_LOGIC_VECTOR (19 downto 0);
				B6 : out STD_LOGIC_VECTOR (19 downto 0);
				B7 : out STD_LOGIC_VECTOR (19 downto 0);
				B8 : out STD_LOGIC_VECTOR (19 downto 0);
				B9 : out STD_LOGIC_VECTOR (19 downto 0);
				B10 : out STD_LOGIC_VECTOR (19 downto 0);
				B11 : out STD_LOGIC_VECTOR (19 downto 0);
				B12 : out STD_LOGIC_VECTOR (19 downto 0);
				B13 : out STD_LOGIC_VECTOR (19 downto 0);
				B14 : out STD_LOGIC_VECTOR (19 downto 0);
				B15 : out STD_LOGIC_VECTOR (19 downto 0);
				B16 : out STD_LOGIC_VECTOR (19 downto 0);
				B17 : out STD_LOGIC_VECTOR (19 downto 0);
				B18 : out STD_LOGIC_VECTOR (19 downto 0);
				B19 : out STD_LOGIC_VECTOR (19 downto 0)					
				);
end arm;

architecture Behavioral of arm is

signal Bf_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B1_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B2_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B3_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B4_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B5_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B6_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B7_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B8_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B9_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B10_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B11_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B12_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B13_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B14_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B15_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B16_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B17_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B18_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B19_1 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');

signal Bf_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B1_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B2_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B3_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B4_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B5_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B6_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B7_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B8_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B9_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B10_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B11_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B12_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B13_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B14_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B15_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B16_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B17_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B18_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B19_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');

begin

Process (CLK)
begin
	if (CLK'event and CLK='1') then
	
		----------------- RESET -------------------------
		if (RST='1') then 
				Bf_1 <= (others => '0');         
				B1_1 <= (others => '0');		
				B2_1 <= (others => '0');
				B3_1 <= (others => '0');
				B4_1 <= (others => '0');
				B5_1 <= (others => '0');
				B6_1 <= (others => '0');
				B7_1 <= (others => '0');
				B8_1 <= (others => '0');
				B9_1 <= (others => '0');
				B10_1 <= (others => '0');
				B11_1 <= (others => '0');
				B12_1 <= (others => '0');
				B13_1 <= (others => '0');
				B14_1 <= (others => '0');
				B15_1 <= (others => '0');
				B16_1 <= (others => '0');
				B17_1 <= (others => '0');
				B18_1 <= (others => '0');
				B19_1 <= (others => '0');
				
		else

				Bf_1 <= "00"& INC;         									-- frecuencia fundamental
				B1_1 <= conv_std_logic_vector (INCe*2,20);				-- primer armonico
				B2_1 <= conv_std_logic_vector (INCe*3,20);
				B3_1 <= conv_std_logic_vector (INCe*4,20);
				B4_1 <= conv_std_logic_vector (INCe*5,20);
				B5_1 <= conv_std_logic_vector (INCe*6,20);
				B6_1 <= conv_std_logic_vector (INCe*7,20);
				B7_1 <= conv_std_logic_vector (INCe*8,20);
				B8_1 <= conv_std_logic_vector (INCe*9,20);
				B9_1 <= conv_std_logic_vector (INCe*10,20);
				B10_1 <= conv_std_logic_vector (INCe*11,20);
				B11_1 <= conv_std_logic_vector (INCe*12,20);
				B12_1 <= conv_std_logic_vector (INCe*13,20);
				B13_1 <= conv_std_logic_vector (INCe*14,20);
				B14_1 <= conv_std_logic_vector (INCe*15,20);
				B15_1 <= conv_std_logic_vector (INCe*16,20);
				B16_1 <= conv_std_logic_vector (INCe*17,20);
				B17_1 <= conv_std_logic_vector (INCe*18,20);
				B18_1 <= conv_std_logic_vector (INCe*19,20);
				B19_1 <= conv_std_logic_vector (INCe*20,20);
				
		end if;
	end if;
end Process;

Bf <= Bf_1;
B1 <= B1_1;
B2 <= B2_1;
B3 <= B3_1;
B4 <= B4_1;
B5 <= B5_1;
B6 <= B6_1;
B7 <= B7_1;
B8 <= B8_1;
B9 <= B9_1;
B10 <= B10_1;
B11 <= B11_1;
B12 <= B12_1;
B13 <= B13_1;
B14 <= B14_1;
B15 <= B15_1;
B16 <= B16_1;
B17 <= B17_1;
B18 <= B18_1;
B19 <= B19_1;

end Behavioral;

