library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sumfin is
    Port ( 	Ent1 : in STD_LOGIC_VECTOR (23 downto 0);
				Ent1_2 : in STD_LOGIC_VECTOR (23 downto 0);
				Ent2 : in STD_LOGIC_VECTOR (23 downto 0);
				Ent2_2 : in STD_LOGIC_VECTOR (23 downto 0);
				Sal1 : out STD_LOGIC_VECTOR (23 downto 0);
				Sal2 : out STD_LOGIC_VECTOR (23 downto 0)
				);
end sumfin;

architecture Behavioral of sumfin is

begin

Sal1 <= Ent1 + Ent2;
Sal2 <= Ent1_2 + Ent2_2;

end Behavioral;

