library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.componentes.ALL;

entity proyecto is 
	Port ( 	CLK : in  STD_LOGIC;															-- reloj a 50MHz
				notas : in STD_LOGIC_VECTOR (11 downto 0);  		
				notas_int : in STD_LOGIC_VECTOR (11 downto 0); 
				num_inst : in STD_LOGIC_VECTOR (1 downto 0);
				en : in STD_LOGIC;
				sel : IN std_logic;
				RST : in STD_LOGIC;
				INIT : IN std_logic; 
				W_EN : IN std_logic;
							LED_config : out STD_LOGIC_VECTOR (2 downto 0);
			LED_modo : out std_logic;	
			LED_inst : out STD_LOGIC_VECTOR (1 downto 0);
--				sim : out STD_LOGIC_VECTOR (23 downto 0);								---------SOLO SIMULACIONES--------
				sal_LED : out  STD_LOGIC_VECTOR (11 downto 0);
				pulse_48KHz : OUT std_logic; 												-- sample sync pulse
				AUD_MCLK : OUT std_logic; 													-- codec master clock input
				AUD_BCLK : OUT std_logic; 													-- digital audio bit clock
				AUD_DACDAT : OUT std_logic; 												-- DAC data lines
				AUD_DACLRCK : OUT std_logic; 												-- DAC data left/right select
				I2C_SDAT : OUT std_logic; 													-- serial interface data line
				I2C_SCLK : OUT std_logic	  												-- serial interface clock
				);
end proyecto;   

architecture Behavioral of proyecto is

signal CLK2 : STD_LOGIC;
signal CLK3 : STD_LOGIC;
signal CLK4 : STD_LOGIC;

signal des : STD_LOGIC_VECTOR (11 downto 0); 
signal notas_inv : STD_LOGIC_VECTOR (11 downto 0); 

signal Sintaud : STD_LOGIC_VECTOR (23 downto 0);
signal Sintaud2 : STD_LOGIC_VECTOR (23 downto 0);

signal f1 : STD_LOGIC_VECTOR (8 downto 0);
signal f2 : STD_LOGIC_VECTOR (8 downto 0);
signal f3 : STD_LOGIC_VECTOR (8 downto 0);
signal f4 : STD_LOGIC_VECTOR (8 downto 0);
signal f5 : STD_LOGIC_VECTOR (8 downto 0);
signal f6 : STD_LOGIC_VECTOR (8 downto 0);
signal f7 : STD_LOGIC_VECTOR (8 downto 0);
signal f8 : STD_LOGIC_VECTOR (8 downto 0);
signal f9 : STD_LOGIC_VECTOR (8 downto 0);
signal f10 : STD_LOGIC_VECTOR (8 downto 0);
signal f11 : STD_LOGIC_VECTOR (8 downto 0);
signal f12 : STD_LOGIC_VECTOR (8 downto 0);
signal f13 : STD_LOGIC_VECTOR (8 downto 0);
signal f14 : STD_LOGIC_VECTOR (8 downto 0);
signal f15 : STD_LOGIC_VECTOR (8 downto 0);
signal f16 : STD_LOGIC_VECTOR (8 downto 0);
signal f17 : STD_LOGIC_VECTOR (8 downto 0);
signal f18 : STD_LOGIC_VECTOR (8 downto 0);
signal f19 : STD_LOGIC_VECTOR (8 downto 0);
	
signal af : STD_LOGIC_VECTOR (7 downto 0);
signal a1 : STD_LOGIC_VECTOR (7 downto 0);								
signal a2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a3 : STD_LOGIC_VECTOR (7 downto 0);								
signal a4 : STD_LOGIC_VECTOR (7 downto 0);								
signal a5 : STD_LOGIC_VECTOR (7 downto 0);								
signal a6 : STD_LOGIC_VECTOR (7 downto 0);								
signal a7 : STD_LOGIC_VECTOR (7 downto 0);								
signal a8 : STD_LOGIC_VECTOR (7 downto 0);								
signal a9 : STD_LOGIC_VECTOR (7 downto 0);								
signal a10 : STD_LOGIC_VECTOR (7 downto 0);								
signal a11 : STD_LOGIC_VECTOR (7 downto 0);								
signal a12 : STD_LOGIC_VECTOR (7 downto 0);								
signal a13 : STD_LOGIC_VECTOR (7 downto 0);								
signal a14 : STD_LOGIC_VECTOR (7 downto 0);								
signal a15 : STD_LOGIC_VECTOR (7 downto 0);								
signal a16 : STD_LOGIC_VECTOR (7 downto 0);								
signal a17 : STD_LOGIC_VECTOR (7 downto 0);								
signal a18 : STD_LOGIC_VECTOR (7 downto 0);								
signal a19 : STD_LOGIC_VECTOR (7 downto 0);

signal cont : STD_LOGIC_VECTOR (4 downto 0);

signal ince : integer;
signal inc : STD_LOGIC_VECTOR (17 downto 0);	

signal armf : STD_LOGIC_VECTOR (19 downto 0);
signal arm1 : STD_LOGIC_VECTOR (19 downto 0);
signal arm2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm3 : STD_LOGIC_VECTOR (19 downto 0);
signal arm4 : STD_LOGIC_VECTOR (19 downto 0);
signal arm5 : STD_LOGIC_VECTOR (19 downto 0);
signal arm6 : STD_LOGIC_VECTOR (19 downto 0);
signal arm7 : STD_LOGIC_VECTOR (19 downto 0);
signal arm8 : STD_LOGIC_VECTOR (19 downto 0);
signal arm9 : STD_LOGIC_VECTOR (19 downto 0);
signal arm10 : STD_LOGIC_VECTOR (19 downto 0);
signal arm11 : STD_LOGIC_VECTOR (19 downto 0);
signal arm12 : STD_LOGIC_VECTOR (19 downto 0);
signal arm13 : STD_LOGIC_VECTOR (19 downto 0);
signal arm14 : STD_LOGIC_VECTOR (19 downto 0);
signal arm15 : STD_LOGIC_VECTOR (19 downto 0);
signal arm16 : STD_LOGIC_VECTOR (19 downto 0);
signal arm17 : STD_LOGIC_VECTOR (19 downto 0);
signal arm18 : STD_LOGIC_VECTOR (19 downto 0);
signal arm19 : STD_LOGIC_VECTOR (19 downto 0);

signal Bf : STD_LOGIC_VECTOR (19 downto 0);
signal B1 : STD_LOGIC_VECTOR (19 downto 0);
signal B2 : STD_LOGIC_VECTOR (19 downto 0);
signal B3 : STD_LOGIC_VECTOR (19 downto 0);
signal B4 : STD_LOGIC_VECTOR (19 downto 0);
signal B5 : STD_LOGIC_VECTOR (19 downto 0);
signal B6 : STD_LOGIC_VECTOR (19 downto 0);
signal B7 : STD_LOGIC_VECTOR (19 downto 0);
signal B8 : STD_LOGIC_VECTOR (19 downto 0);
signal B9 : STD_LOGIC_VECTOR (19 downto 0);
signal B10 : STD_LOGIC_VECTOR (19 downto 0);
signal B11 : STD_LOGIC_VECTOR (19 downto 0);
signal B12 : STD_LOGIC_VECTOR (19 downto 0);
signal B13 : STD_LOGIC_VECTOR (19 downto 0);
signal B14 : STD_LOGIC_VECTOR (19 downto 0);
signal B15 : STD_LOGIC_VECTOR (19 downto 0);
signal B16 : STD_LOGIC_VECTOR (19 downto 0);
signal B17 : STD_LOGIC_VECTOR (19 downto 0);
signal B18 : STD_LOGIC_VECTOR (19 downto 0);
signal B19 : STD_LOGIC_VECTOR (19 downto 0);

signal Bf_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B1_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B2_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B3_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B4_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B5_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B6_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B7_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B8_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B9_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B10_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B11_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B12_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B13_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B14_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B15_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B16_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B17_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B18_3 : STD_LOGIC_VECTOR (8 downto 0);
signal B19_3 : STD_LOGIC_VECTOR (8 downto 0);

signal Bf_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B1_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B2_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B3_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B4_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B5_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B6_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B7_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B8_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B9_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B10_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B11_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B12_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B13_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B14_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B15_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B16_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B17_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B18_4 : STD_LOGIC_VECTOR (8 downto 0);
signal B19_4 : STD_LOGIC_VECTOR (8 downto 0);

signal dir_mem : STD_LOGIC_VECTOR (8 downto 0);
signal sensal : integer;

signal Bf_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B1_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B2_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B3_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B4_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B5_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B6_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B7_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B8_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B9_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B10_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B11_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B12_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B13_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B14_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B15_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B16_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B17_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B18_5 : STD_LOGIC_VECTOR (7 downto 0);
signal B19_5 : STD_LOGIC_VECTOR (7 downto 0);

signal Bf_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B1_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B2_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B3_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B4_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B5_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B6_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B7_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B8_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B9_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B10_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B11_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B12_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B13_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B14_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B15_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B16_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B17_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B18_FF : STD_LOGIC_VECTOR (7 downto 0);
signal B19_FF : STD_LOGIC_VECTOR (7 downto 0);

signal Bf_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B1_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B2_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B3_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B4_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B5_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B6_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B7_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B8_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B9_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B10_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B11_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B12_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B13_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B14_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B15_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B16_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B17_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B18_6 : STD_LOGIC_VECTOR (15 downto 0);
signal B19_6 : STD_LOGIC_VECTOR (15 downto 0);

signal Bf_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B1_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B2_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B3_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B4_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B5_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B6_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B7_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B8_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B9_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B10_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B11_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B12_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B13_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B14_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B15_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B16_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B17_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B18_7 : STD_LOGIC_VECTOR (15 downto 0);
signal B19_7 : STD_LOGIC_VECTOR (15 downto 0);
				
signal Salsum : STD_LOGIC_VECTOR (19 downto 0);

signal notasent : STD_LOGIC_VECTOR (11 downto 0); 
signal notas_sel : STD_LOGIC_VECTOR (11 downto 0); 

signal nota1 : STD_LOGIC_VECTOR (4 downto 0);
signal nota2 : STD_LOGIC_VECTOR (4 downto 0);

signal Sal1 : STD_LOGIC_VECTOR (23 downto 0);
signal Sal2 : STD_LOGIC_VECTOR (23 downto 0);

signal Sintaud_2 : STD_LOGIC_VECTOR (23 downto 0);
signal Sintaud2_2 : STD_LOGIC_VECTOR (23 downto 0);

signal f1_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f2_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f5_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f6_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f7_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f8_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f9_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f10_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f11_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f12_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f13_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f14_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f15_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f16_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f17_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f18_2 : STD_LOGIC_VECTOR (8 downto 0);
signal f19_2 : STD_LOGIC_VECTOR (8 downto 0);
	
signal af_2 : STD_LOGIC_VECTOR (7 downto 0);
signal a1_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a2_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a3_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a4_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a5_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a6_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a7_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a8_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a9_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a10_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a11_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a12_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a13_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a14_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a15_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a16_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a17_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a18_2 : STD_LOGIC_VECTOR (7 downto 0);								
signal a19_2 : STD_LOGIC_VECTOR (7 downto 0);

signal ince_2 : integer;
signal inc_2 : STD_LOGIC_VECTOR (17 downto 0);	

signal armf_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm1_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm2_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm3_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm4_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm5_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm6_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm7_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm8_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm9_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm10_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm11_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm12_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm13_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm14_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm15_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm16_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm17_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm18_2 : STD_LOGIC_VECTOR (19 downto 0);
signal arm19_2 : STD_LOGIC_VECTOR (19 downto 0);

signal Bf_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B1_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B2_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B3_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B4_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B5_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B6_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B7_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B8_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B9_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B10_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B11_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B12_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B13_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B14_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B15_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B16_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B17_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B18_2 : STD_LOGIC_VECTOR (19 downto 0);
signal B19_2 : STD_LOGIC_VECTOR (19 downto 0);

signal Bf_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B1_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B2_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B3_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B4_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B5_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B6_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B7_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B8_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B9_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B10_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B11_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B12_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B13_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B14_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B15_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B16_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B17_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B18_3_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B19_3_2 : STD_LOGIC_VECTOR (8 downto 0);

signal Bf_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B1_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B2_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B3_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B4_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B5_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B6_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B7_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B8_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B9_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B10_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B11_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B12_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B13_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B14_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B15_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B16_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B17_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B18_4_2 : STD_LOGIC_VECTOR (8 downto 0);
signal B19_4_2 : STD_LOGIC_VECTOR (8 downto 0);

signal dir_mem_2 : STD_LOGIC_VECTOR (8 downto 0);
signal sensal_2 : integer;

signal Bf_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B1_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B2_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B3_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B4_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B5_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B6_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B7_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B8_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B9_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B10_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B11_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B12_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B13_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B14_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B15_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B16_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B17_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B18_5_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B19_5_2 : STD_LOGIC_VECTOR (7 downto 0);

signal Bf_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B1_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B2_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B3_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B4_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B5_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B6_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B7_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B8_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B9_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B10_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B11_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B12_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B13_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B14_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B15_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B16_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B17_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B18_FF_2 : STD_LOGIC_VECTOR (7 downto 0);
signal B19_FF_2 : STD_LOGIC_VECTOR (7 downto 0);

signal Bf_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B1_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B2_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B3_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B4_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B5_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B6_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B7_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B8_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B9_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B10_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B11_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B12_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B13_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B14_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B15_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B16_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B17_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B18_6_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B19_6_2 : STD_LOGIC_VECTOR (15 downto 0);

signal Bf_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B1_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B2_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B3_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B4_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B5_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B6_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B7_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B8_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B9_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B10_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B11_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B12_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B13_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B14_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B15_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B16_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B17_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B18_7_2 : STD_LOGIC_VECTOR (15 downto 0);
signal B19_7_2 : STD_LOGIC_VECTOR (15 downto 0);

signal Salsum_2 : STD_LOGIC_VECTOR (19 downto 0);

begin

U1 : divisor1 Port map (CLK, RST, CLK2);													--divisor aprox 48000Hz

U2 : divisor2 Port map (CLK, RST, CLK3);													--divisor 25MHz

U3 : divisor3 Port map (CLK, RST, CLK4);													--divisor 1MHz aprox 1.008MHz

U4 : g00_audio_interface	PORT map(Sal1 , Sal2, CLK3, RST,INIT, W_EN, 			--interfaz de audio
												pulse_48KHz, AUD_MCLK, AUD_BCLK, 
												AUD_DACDAT, AUD_DACLRCK, I2C_SDAT, 
												I2C_SCLK );
												
--U5 : LED Port map (nota1, sal_LED);															--iluminaci�n de LEDs segun nota tocada
U5 : LED2 Port map ( notas_sel,sal_LED );

U6 : fase Port map (CLK2,nota1,num_inst,f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,
						  f11,f12,f13,f14,f15,f16,f17,f18,f19);
						  
U7 : amplitud Port map (CLK2,nota1,num_inst,af,a1,a2,a3,a4,a5,a6,a7,a8,
								a9,a10,a11,a12,a13,a14,a15,a16,a17,a18,a19);
								
U8 : control Port map (CLK4,RST,cont);														-- se�ales de control

U9 : incrementos Port map (CLK2,nota1,num_inst,ince,inc); 

U10 : arm Port map (CLK2,nota1,num_inst,RST,ince,inc,armf,arm1,arm2,				-- Calculo armonicos
						  arm3,arm4,arm5,arm6,arm7,arm8,arm9,arm10,arm11,arm12,
						  arm13,arm14,arm15,arm16,arm17,arm18,arm19);
						  
U11 : acum Port map (CLK2,RST,armf,arm1,arm2,arm3,arm4,arm5,arm6,arm7,			-- acumulador
							arm8,arm9,arm10,arm11,arm12,arm13,arm14,arm15,arm16,
							arm17,arm18,arm19,Bf,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,
							B11,B12,B13,B14,B15,B16,B17,B18,B19);
							
U12 : sumfas Port map (f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,		-- suma fase
							  f16,f17,f18,f19,Bf,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,
							  B11,B12,B13,B14,B15,B16,B17,B18,B19,Bf_3,B1_3,B2_3,
							  B3_3,B4_3,B5_3,B6_3,B7_3,B8_3,B9_3,B10_3,B11_3,B12_3,
							  B13_3,B14_3,B15_3,B16_3,B17_3,B18_3,B19_3);

U13 : FF1 Port map (CLK2,Bf_3,B1_3,B2_3,B3_3,B4_3,B5_3,B6_3,B7_3,B8_3,B9_3,	-- FF antes de MUX a 48000
						  B10_3,B11_3,B12_3,B13_3,B14_3,B15_3,B16_3,B17_3,B18_3,
						  B19_3,Bf_4,B1_4,B2_4,B3_4,B4_4,B5_4,B6_4,B7_4,B8_4,B9_4,
						  B10_4,B11_4,B12_4,B13_4,B14_4,B15_4,B16_4,B17_4,B18_4,
						  B19_4);
						  
U14 : mux1 Port map (CLK4,cont,Bf_4,B1_4,B2_4,B3_4,B4_4,B5_4,B6_4,B7_4,B8_4,	-- MUX a 48000 * 21
							B9_4,B10_4,B11_4,B12_4,B13_4,B14_4,B15_4,B16_4,B17_4,
							B18_4,B19_4,dir_mem);

U15 : sen Port map (dir_mem,sensal);

U16 : DMUX Port map (CLK4,cont,sensal,Bf_5,B1_5,B2_5,B3_5,B4_5,B5_5,B6_5,		-- DEMUX a 48000 * 21
							B7_5,B8_5,B9_5,B10_5,B11_5,B12_5,B13_5,B14_5,B15_5,
							B16_5,B17_5,B18_5,B19_5);

U17 : FF2 Port map (CLK4,cont,Bf_5,B1_5,B2_5,B3_5,B4_5,B5_5,B6_5,B7_5,B8_5,	-- FF a 48000*21
						  B9_5,B10_5,B11_5,B12_5,B13_5,B14_5,B15_5,B16_5,B17_5,
						  B18_5,B19_5,Bf_FF,B1_FF,B2_FF,B3_FF,B4_FF,B5_FF,B6_FF,
	 					  B7_FF,B8_FF,B9_FF,B10_FF,B11_FF,B12_FF,B13_FF,B14_FF,
						  B15_FF,B16_FF,B17_FF,B18_FF,B19_FF);

U18 : mult Port map (af,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,	-- multiplicar por la amplitud
							a16,a17,a18,a19,Bf_FF,B1_FF,B2_FF,B3_FF,B4_FF,B5_FF,
							B6_FF,B7_FF,B8_FF,B9_FF,B10_FF,B11_FF,B12_FF,B13_FF,
							B14_FF,B15_FF,B16_FF,B17_FF,B18_FF,B19_FF,Bf_6,B1_6,
							B2_6,B3_6,B4_6,B5_6,B6_6,B7_6,B8_6,B9_6,B10_6,B11_6,
							B12_6,B13_6,B14_6,B15_6,B16_6,B17_6,B18_6,B19_6);

U19 : offset Port map (af,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,
							  a15,a16,a17,a18,a19,Bf_6,B1_6,B2_6,B3_6,B4_6,B5_6,
							  B6_6,B7_6,B8_6,B9_6,B10_6,B11_6,B12_6,B13_6,B14_6,
							  B15_6,B16_6,B17_6,B18_6,B19_6,Bf_7,B1_7,B2_7,B3_7,
							  B4_7,B5_7,B6_7,B7_7,B8_7,B9_7,B10_7,B11_7,B12_7,
							  B13_7,B14_7,B15_7,B16_7,B17_7,B18_7,B19_7);
							  
U20 : suma Port map (Bf_7,B1_7,B2_7,B3_7,B4_7,B5_7,B6_7,B7_7,B8_7,B9_7,B10_7,	-- suma frecuencia fundamental y armonicos
							B11_7,B12_7,B13_7,B14_7,B15_7,B16_7,B17_7,B18_7,B19_7,
							Salsum);
							
U21 : ajuste Port map (Salsum,Sintaud,Sintaud2);										-- ajuste del volumen

U42:  invertir Port map ( CLK2,notas,notas_inv); 

U40 : deteccion Port map (CLK2,notas_inv,en,des); 														-- detectar fundidos

U22 : arp Port map (CLK2,notas_inv,des,notasent); 											-- desactivar se�ales

U41 : seleccion Port map (sel,clk2,notasent,notas_int,notas_sel); 				-- seleccionar notas arp o notas interupt

--U41 : seleccion Port map (sel,clk2,notas_inv,notas_int,notas_sel); 				-- seleccionar notas arp o notas interupt

U23 : calc_notas Port map (CLK2,notas_sel,nota1,nota2); 								-- Convertir se�ales a notas

U24 : fase Port map (CLK2,nota2,num_inst,f1_2,f2_2,f3_2,f4_2,f5_2,f6_2,f7_2,
							f8_2,f9_2,f10_2,f11_2,f12_2,f13_2,f14_2,f15_2,f16_2,
							f17_2,f18_2,f19_2);
						  
U25 : amplitud Port map (CLK2,nota2,num_inst,af_2,a1_2,a2_2,a3_2,a4_2,a5_2,
								 a6_2,a7_2,a8_2,a9_2,a10_2,a11_2,a12_2,a13_2,a14_2,
								 a15_2,a16_2,a17_2,a18_2,a19_2);
								
U26 : incrementos Port map (CLK2,nota2,num_inst,ince_2,inc_2); 

U27 : arm Port map (CLK2,nota2,num_inst,RST,ince_2,inc_2,armf_2,arm1_2,			-- Calculo armonicos
						  arm2_2,	arm3_2,arm4_2,arm5_2,arm6_2,arm7_2,arm8_2,
						  arm9_2,arm10_2,arm11_2,arm12_2,arm13_2,arm14_2,arm15_2,
						  arm16_2,arm17_2,arm18_2,arm19_2);
						  
U28 : acum Port map (CLK2,RST,armf_2,arm1_2,arm2_2,arm3_2,arm4_2,arm5_2,		-- acumulador
							arm6_2,arm7_2,arm8_2,arm9_2,arm10_2,arm11_2,arm12_2,
							arm13_2,arm14_2,arm15_2,arm16_2,arm17_2,arm18_2,arm19_2,
							Bf_2,B1_2,B2_2,B3_2,B4_2,B5_2,B6_2,B7_2,B8_2,B9_2,B10_2,
							B11_2,B12_2,B13_2,B14_2,B15_2,B16_2,B17_2,B18_2,B19_2);
							
U29 : sumfas Port map (f1_2,f2_2,f3_2,f4_2,f5_2,f6_2,f7_2,f8_2,f9_2,f10_2,		-- suma fase
							  f11_2,f12_2,f13_2,f14_2,f15_2,f16_2,f17_2,f18_2,f19_2,
							  Bf_2,B1_2,B2_2,B3_2,B4_2,B5_2,B6_2,B7_2,B8_2,B9_2,B10_2,
							  B11_2,B12_2,B13_2,B14_2,B15_2,B16_2,B17_2,B18_2,B19_2,
							  Bf_3_2,B1_3_2,B2_3_2,B3_3_2,B4_3_2,B5_3_2,B6_3_2,B7_3_2,
							  B8_3_2,B9_3_2,B10_3_2,B11_3_2,B12_3_2,B13_3_2,B14_3_2,
							  B15_3_2,B16_3_2,B17_3_2,B18_3_2,B19_3_2);

U30 : FF1 Port map (CLK2,Bf_3_2,B1_3_2,B2_3_2,B3_3_2,B4_3_2,B5_3_2,B6_3_2,		-- FF antes de MUX a 48000
						  B7_3_2,B8_3_2,B9_3_2,B10_3_2,B11_3_2,B12_3_2,B13_3_2,
						  B14_3_2,B15_3_2,B16_3_2,B17_3_2,B18_3_2,B19_3_2,Bf_4_2,
						  B1_4_2,B2_4_2,B3_4_2,B4_4_2,B5_4_2,B6_4_2,B7_4_2,B8_4_2,
						  B9_4_2,B10_4_2,B11_4_2,B12_4_2,B13_4_2,B14_4_2,B15_4_2,
						  B16_4_2,B17_4_2,B18_4_2,B19_4_2);
						  
U31 : mux1 Port map (CLK4,cont,Bf_4_2,B1_4_2,B2_4_2,B3_4_2,B4_4_2,B5_4_2,		-- MUX a 48000 * 21
							B6_4_2,B7_4_2,B8_4_2,B9_4_2,B10_4_2,B11_4_2,B12_4_2,
							B13_4_2,B14_4_2,B15_4_2,B16_4_2,B17_4_2,B18_4_2,B19_4_2,
							dir_mem_2);

U32 : sen Port map (dir_mem_2,sensal_2);

U33 : DMUX Port map (CLK4,cont,sensal_2,Bf_5_2,B1_5_2,B2_5_2,B3_5_2,B4_5_2,	-- DEMUX a 48000 * 21
							B5_5_2,B6_5_2,B7_5_2,B8_5_2,B9_5_2,B10_5_2,B11_5_2,
							B12_5_2,B13_5_2,B14_5_2,B15_5_2,B16_5_2,B17_5_2,B18_5_2,
							B19_5_2);

U34 : FF2 Port map (CLK4,cont,Bf_5_2,B1_5_2,B2_5_2,B3_5_2,B4_5_2,B5_5_2,		-- FF a 48000*21
						  B6_5_2,B7_5_2,B8_5_2,	B9_5_2,B10_5_2,B11_5_2,B12_5_2,
						  B13_5_2,B14_5_2,B15_5_2,B16_5_2,B17_5_2,B18_5_2,B19_5_2,
						  Bf_FF_2,B1_FF_2,B2_FF_2,B3_FF_2,B4_FF_2,B5_FF_2,B6_FF_2,
	 					  B7_FF_2,B8_FF_2,B9_FF_2,B10_FF_2,B11_FF_2,B12_FF_2,
						  B13_FF_2,B14_FF_2,B15_FF_2,B16_FF_2,B17_FF_2,B18_FF_2,
						  B19_FF_2);

U35 : mult Port map (af_2,a1_2,a2_2,a3_2,a4_2,a5_2,a6_2,a7_2,a8_2,a9_2,a10_2,	-- multiplicar por la amplitud
							a11_2,a12_2,a13_2,a14_2,a15_2,a16_2,a17_2,a18_2,a19_2,
							Bf_FF_2,B1_FF_2,B2_FF_2,B3_FF_2,B4_FF_2,B5_FF_2,B6_FF_2,
							B7_FF_2,B8_FF_2,B9_FF_2,B10_FF_2,B11_FF_2,B12_FF_2,
							B13_FF_2,B14_FF_2,B15_FF_2,B16_FF_2,B17_FF_2,B18_FF_2,
							B19_FF_2,Bf_6_2,B1_6_2,B2_6_2,B3_6_2,B4_6_2,B5_6_2,B6_6_2,
							B7_6_2,B8_6_2,B9_6_2,B10_6_2,B11_6_2,B12_6_2,B13_6_2,
							B14_6_2,B15_6_2,B16_6_2,B17_6_2,B18_6_2,B19_6_2);

U36 : offset Port map (af_2,a1_2,a2_2,a3_2,a4_2,a5_2,a6_2,a7_2,a8_2,a9_2,a10_2,
							  a11_2,a12_2,a13_2,a14_2,a15_2,a16_2,a17_2,a18_2,a19_2,
							  Bf_6_2,B1_6_2,B2_6_2,B3_6_2,B4_6_2,B5_6_2,B6_6_2,B7_6_2,
							  B8_6_2,B9_6_2,B10_6_2,B11_6_2,B12_6_2,B13_6_2,B14_6_2,
							  B15_6_2,B16_6_2,B17_6_2,B18_6_2,B19_6_2,Bf_7_2,B1_7_2,
							  B2_7_2,B3_7_2,B4_7_2,B5_7_2,B6_7_2,B7_7_2,B8_7_2,B9_7_2,
							  B10_7_2,B11_7_2,B12_7_2,B13_7_2,B14_7_2,B15_7_2,B16_7_2,
							  B17_7_2,B18_7_2,B19_7_2);
							  
U37 : suma Port map (Bf_7_2,B1_7_2,B2_7_2,B3_7_2,B4_7_2,B5_7_2,B6_7_2,B7_7_2,	-- suma frecuencia fundamental y armonicos
							B8_7_2,B9_7_2,B10_7_2,B11_7_2,B12_7_2,B13_7_2,B14_7_2,
							B15_7_2,B16_7_2,B17_7_2,B18_7_2,B19_7_2,Salsum_2);
							
U38 : ajuste Port map (Salsum_2,Sintaud_2,Sintaud2_2);								-- ajuste del volumen

U39 : sumfin Port map (Sintaud,Sintaud2,Sintaud_2,Sintaud2_2,Sal1,Sal2);		-- suma de las dos notas

--sim <= Sal1;																						-- para las simulaciones

U43 : LED3 Port map ( INIT,CLK, W_EN , RST ,sel, num_inst,LED_config,LED_modo,LED_inst);

end Behavioral;

