library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity arp is
    Port ( 	CLK : in  STD_LOGIC;                                    	-- Tiene que funcionar a 48000
				notas : in STD_LOGIC_VECTOR (11 downto 0); 					-- Notas arpa
				des : in STD_LOGIC_VECTOR (11 downto 0);						-- Interruptores para desactivar notas
				Sal : out STD_LOGIC_VECTOR (11 downto 0)						
				); 
end arp;

architecture Behavioral of arp is

signal Salint : STD_LOGIC_VECTOR (11 downto 0):= (others=>'0');

begin

Process (CLK)
begin
	if (CLK'event and CLK='1') then
		if	(des(11)='1') then Salint(11) <= notas(11);
		else Salint(11)<='0';
		end if;
		
		if	(des(10)='1') then Salint(10) <= notas(10);
		else Salint(10)<='0';
		end if;
		
		if	(des(9)='1') then Salint(9) <= notas(9);
		else Salint(9)<='0';
		end if;
		
		if	(des(8)='1') then Salint(8) <= notas(8);
		else Salint(8)<='0';
		end if;
		
		if	(des(7)='1') then Salint(7) <= notas(7);
		else Salint(7)<='0';
		end if;
		
		if	(des(6)='1') then Salint(6) <= notas(6);
		else Salint(6)<='0';
		end if;
		
		if	(des(5)='1') then Salint(5) <= notas(5);
		else Salint(5)<='0';
		end if;
		
		if	(des(4)='1') then Salint(4) <= notas(4);
		else Salint(4)<='0';
		end if;
		
		if	(des(3)='1') then Salint(3) <= notas(3);
		else Salint(3)<='0';
		end if;
		
		if	(des(2)='1') then Salint(2) <= notas(2);
		else Salint(2)<='0';
		end if;
		
		if	(des(1)='1') then Salint(1) <= notas(1);
		else Salint(1)<='0';
		end if;
		
		if	(des(0)='1') then Salint(0) <= notas(0);
		else Salint(0)<='0';
		end if;
	end if;
end process;
		
Sal <= Salint;		

end Behavioral;

