
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LED3 is
    Port ( 	INIT : IN std_logic; 
			CLK : IN std_logic; 
           W_EN : IN std_logic;
           RST : in STD_LOGIC;
           sel : IN std_logic;									--modo
           num_inst : in STD_LOGIC_VECTOR (1 downto 0);
			LED_config : out STD_LOGIC_VECTOR (2 downto 0);
			LED_modo : out std_logic;	
			LED_inst : out STD_LOGIC_VECTOR (1 downto 0));
end LED3;

architecture Behavioral of LED3 is

signal inter : STD_LOGIC_VECTOR (2 downto 0);
signal inter2 : STD_LOGIC_VECTOR (2 downto 0);

begin

LED_modo <= sel;
LED_inst <= num_inst;

inter <= INIT & W_EN & RST;
Process (CLK)
begin
	if (CLK'event and CLK='1') then
		if	(inter="000") then inter2 <= "101";
		elsif (inter="001") then inter2 <= "000";
		elsif (inter="010") then inter2 <= "111";
		elsif (inter="011") then inter2 <= "000";
		elsif (inter="100") then inter2 <= "001";
		elsif (inter="101") then inter2 <= "000";
		elsif (inter="110") then inter2 <= "011";
		elsif (inter="111") then inter2 <= "000";
		end if;
	end if;
end process;

LED_config <= inter2;
end Behavioral;

