library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity acum is
    Port ( 	CLK : in  STD_LOGIC;                                    -- Tiene que funcionar a 48000
				RST : in STD_LOGIC;
				Bf_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B1_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B2_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B3_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B4_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B5_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B6_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B7_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B8_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B9_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B10_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B11_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B12_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B13_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B14_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B15_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B16_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B17_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B18_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B19_1 : in STD_LOGIC_VECTOR (19 downto 0);
				Bf : out STD_LOGIC_VECTOR (19 downto 0);
				B1 : out STD_LOGIC_VECTOR (19 downto 0);
				B2 : out STD_LOGIC_VECTOR (19 downto 0);
				B3 : out STD_LOGIC_VECTOR (19 downto 0);
				B4 : out STD_LOGIC_VECTOR (19 downto 0);
				B5 : out STD_LOGIC_VECTOR (19 downto 0);
				B6 : out STD_LOGIC_VECTOR (19 downto 0);
				B7 : out STD_LOGIC_VECTOR (19 downto 0);
				B8 : out STD_LOGIC_VECTOR (19 downto 0);
				B9 : out STD_LOGIC_VECTOR (19 downto 0);
				B10 : out STD_LOGIC_VECTOR (19 downto 0);
				B11 : out STD_LOGIC_VECTOR (19 downto 0);
				B12 : out STD_LOGIC_VECTOR (19 downto 0);
				B13 : out STD_LOGIC_VECTOR (19 downto 0);
				B14 : out STD_LOGIC_VECTOR (19 downto 0);
				B15 : out STD_LOGIC_VECTOR (19 downto 0);
				B16 : out STD_LOGIC_VECTOR (19 downto 0);
				B17 : out STD_LOGIC_VECTOR (19 downto 0);
				B18 : out STD_LOGIC_VECTOR (19 downto 0);
				B19 : out STD_LOGIC_VECTOR (19 downto 0)	
				);
end acum;

architecture Behavioral of acum is

signal Bf_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B1_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B2_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B3_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B4_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B5_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B6_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B7_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B8_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B9_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B10_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B11_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B12_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B13_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B14_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B15_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B16_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B17_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B18_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');
signal B19_2 : STD_LOGIC_VECTOR (19 downto 0):= (others=>'0');

begin

Process (CLK)
begin
	if (CLK'event and CLK='1') then
	
		----------------- RESET -------------------------
		if (RST='1') then 		
				Bf_2 <= (others => '0');       
				B1_2 <= (others => '0');
				B2_2 <= (others => '0');
				B3_2 <= (others => '0');
				B4_2 <= (others => '0');
				B5_2 <= (others => '0');
				B6_2 <= (others => '0');
				B7_2 <= (others => '0');
				B8_2 <= (others => '0');
				B9_2 <= (others => '0');
				B10_2 <= (others => '0');
				B11_2 <= (others => '0');
				B12_2 <= (others => '0');
				B13_2 <= (others => '0');
				B14_2 <= (others => '0');
				B15_2 <= (others => '0');
				B16_2 <= (others => '0');
				B17_2 <= (others => '0');
				B18_2 <= (others => '0');
				B19_2 <= (others => '0');				
		else
				Bf_2 <= Bf_2+Bf_1;
				B1_2 <= B1_2+B1_1;
				B2_2 <= B2_2+B2_1;
				B3_2 <= B3_2+B3_1;
				B4_2 <= B4_2+B4_1;
				B5_2 <= B5_2+B5_1;
				B6_2 <= B6_2+B6_1;
				B7_2 <= B7_2+B7_1;
				B8_2 <= B8_2+B8_1;
				B9_2 <= B9_2+B9_1;
				B10_2 <= B10_2+B10_1;
				B11_2 <= B11_2+B11_1;
				B12_2 <= B12_2+B12_1;
				B13_2 <= B13_2+B13_1;
				B14_2 <= B14_2+B14_1;
				B15_2 <= B15_2+B15_1;
				B16_2 <= B16_2+B16_1;
   			B17_2 <= B17_2+B17_1;
				B18_2 <= B18_2+B18_1;
				B19_2 <= B19_2+B19_1;	
		end if;
	end if;
end Process;

Bf <= Bf_2;
B1 <= B1_2;
B2 <= B2_2;
B3 <= B3_2;
B4 <= B4_2;
B5 <= B5_2;
B6 <= B6_2;
B7 <= B7_2;
B8 <= B8_2;
B9 <= B9_2;
B10 <= B10_2;
B11 <= B11_2;
B12 <= B12_2;
B13 <= B13_2;
B14 <= B14_2;
B15 <= B15_2;
B16 <= B16_2;
B17 <= B17_2;
B18 <= B18_2;
B19 <= B19_2;

end Behavioral;

