library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity offset is
    Port ( 	ampfund : in STD_LOGIC_VECTOR (7 downto 0);
				amp1 : in STD_LOGIC_VECTOR (7 downto 0);
				amp2 : in STD_LOGIC_VECTOR (7 downto 0);
				amp3 : in STD_LOGIC_VECTOR (7 downto 0);
				amp4 : in STD_LOGIC_VECTOR (7 downto 0);
				amp5 : in STD_LOGIC_VECTOR (7 downto 0);
				amp6 : in STD_LOGIC_VECTOR (7 downto 0);
				amp7 : in STD_LOGIC_VECTOR (7 downto 0);
				amp8 : in STD_LOGIC_VECTOR (7 downto 0);
				amp9 : in STD_LOGIC_VECTOR (7 downto 0);
				amp10 : in STD_LOGIC_VECTOR (7 downto 0);
				amp11 : in STD_LOGIC_VECTOR (7 downto 0);
				amp12 : in STD_LOGIC_VECTOR (7 downto 0);
				amp13 : in STD_LOGIC_VECTOR (7 downto 0);
				amp14 : in STD_LOGIC_VECTOR (7 downto 0);
				amp15 : in STD_LOGIC_VECTOR (7 downto 0);
				amp16 : in STD_LOGIC_VECTOR (7 downto 0);
				amp17 : in STD_LOGIC_VECTOR (7 downto 0);
				amp18 : in STD_LOGIC_VECTOR (7 downto 0);
				amp19 : in STD_LOGIC_VECTOR (7 downto 0);
				Bf_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B1_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B2_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B3_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B4_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B5_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B6_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B7_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B8_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B9_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B10_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B11_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B12_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B13_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B14_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B15_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B16_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B17_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B18_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B19_6 : in STD_LOGIC_VECTOR (15 downto 0);
				Bf_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B1_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B2_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B3_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B4_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B5_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B6_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B7_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B8_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B9_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B10_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B11_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B12_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B13_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B14_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B15_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B16_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B17_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B18_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B19_7 : out STD_LOGIC_VECTOR (15 downto 0)
				);
end offset;

architecture Behavioral of offset is

signal max1 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal max2 : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal cont : STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal med : STD_LOGIC_VECTOR (7 downto 0):= (others=>'0');
signal divf :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div1 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div2 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div3 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div4 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div5 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div6 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div7 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div8 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div9 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div10 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div11 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div12 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div13 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div14 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div15 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div16 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div17 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div18 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');
signal div19 :  STD_LOGIC_VECTOR (15 downto 0):= (others=>'0');

begin

				max1 <= conv_std_logic_vector(255,8);								-- cambiar dependiendo amplitud maxima mem sen
				max2 <= conv_std_logic_vector(78,8);								-- 156/2 cambiar dependiendo de amplitud maxima entre todos los instrumentos
				cont <= (max1 * max2); 	                                  	-- valor de offset
				med <= conv_std_logic_vector(128,8);								-- 255/2 aprox 128        
				
				divf <= (ampfund * med);												-- sacar punto medio seņal
				div1 <= (amp1 * med);
				div2 <= (amp2 * med);
				div3 <= (amp3 * med);
				div4 <= (amp4 * med);
				div5 <= (amp5 * med);
				div6 <= (amp6 * med);
				div7 <= (amp7 * med);
				div8 <= (amp8 * med);
				div9 <= (amp9 * med);
				div10 <= (amp10 * med);
				div11 <= (amp11 * med);
				div12 <= (amp12 * med);
				div13 <= (amp13 * med);
				div14 <= (amp14 * med);
				div15 <= (amp15 * med);
				div16 <= (amp16 * med);
				div17 <= (amp17 * med);
				div18 <= (amp18 * med);
				div19 <= (amp19 * med);
				
				Bf_7 <= Bf_6 + cont - divf;											-- sumar diferencia
				B1_7 <= B1_6 + cont - div1;
				B2_7 <= B2_6 + cont - div2;
				B3_7 <= B3_6 + cont - div3;
				B4_7 <= B4_6 + cont - div4;
				B5_7 <= B5_6 + cont - div5;
				B6_7 <= B6_6 + cont - div6;
				B7_7 <= B7_6 + cont - div7;
				B8_7 <= B8_6 + cont - div8;
				B9_7 <= B9_6 + cont - div9;
				B10_7 <= B10_6 + cont - div10;
				B11_7 <= B11_6 + cont - div11;
				B12_7 <= B12_6 + cont - div12;
				B13_7 <= B13_6 + cont - div13;
				B14_7 <= B14_6 + cont - div14;
				B15_7 <= B15_6 + cont - div15;
				B16_7 <= B16_6 + cont - div16;
				B17_7 <= B17_6 + cont - div17;
				B18_7 <= B18_6 + cont - div18;
				B19_7 <= B19_6 + cont - div19;

end Behavioral;

