library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mult is
    Port ( 	ampfund : in STD_LOGIC_VECTOR (7 downto 0);
				amp1 : in STD_LOGIC_VECTOR (7 downto 0);
				amp2 : in STD_LOGIC_VECTOR (7 downto 0);
				amp3 : in STD_LOGIC_VECTOR (7 downto 0);
				amp4 : in STD_LOGIC_VECTOR (7 downto 0);
				amp5 : in STD_LOGIC_VECTOR (7 downto 0);
				amp6 : in STD_LOGIC_VECTOR (7 downto 0);
				amp7 : in STD_LOGIC_VECTOR (7 downto 0);
				amp8 : in STD_LOGIC_VECTOR (7 downto 0);
				amp9 : in STD_LOGIC_VECTOR (7 downto 0);
				amp10 : in STD_LOGIC_VECTOR (7 downto 0);
				amp11 : in STD_LOGIC_VECTOR (7 downto 0);
				amp12 : in STD_LOGIC_VECTOR (7 downto 0);
				amp13 : in STD_LOGIC_VECTOR (7 downto 0);
				amp14 : in STD_LOGIC_VECTOR (7 downto 0);
				amp15 : in STD_LOGIC_VECTOR (7 downto 0);
				amp16 : in STD_LOGIC_VECTOR (7 downto 0);
				amp17 : in STD_LOGIC_VECTOR (7 downto 0);
				amp18 : in STD_LOGIC_VECTOR (7 downto 0);
				amp19 : in STD_LOGIC_VECTOR (7 downto 0);
				Bf_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B1_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B2_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B3_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B4_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B5_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B6_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B7_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B8_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B9_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B10_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B11_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B12_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B13_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B14_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B15_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B16_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B17_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B18_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B19_FF : in STD_LOGIC_VECTOR (7 downto 0);
				Bf_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B1_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B2_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B3_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B4_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B5_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B6_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B7_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B8_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B9_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B10_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B11_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B12_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B13_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B14_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B15_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B16_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B17_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B18_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B19_6 : out STD_LOGIC_VECTOR (15 downto 0)
				);
end mult;

architecture Behavioral of mult is

begin

				Bf_6 <= Bf_FF * ampfund;
				B1_6 <= B1_FF * amp1;
				B2_6 <= B2_FF * amp2;
				B3_6 <= B3_FF * amp3;
				B4_6 <= B4_FF * amp4;
				B5_6 <= B5_FF * amp5;
   			B6_6 <= B6_FF * amp6;
				B7_6 <= B7_FF * amp7;
				B8_6 <= B8_FF * amp8;
				B9_6 <= B9_FF * amp9;
				B10_6 <= B10_FF * amp10;
				B11_6 <= B11_FF * amp11;
				B12_6 <= B12_FF * amp12;
				B13_6 <= B13_FF * amp13;
				B14_6 <= B14_FF * amp14;
				B15_6 <= B15_FF * amp15;
				B16_6 <= B16_FF * amp16;
				B17_6 <= B17_FF * amp17;
   			B18_6 <= B18_FF * amp18;
				B19_6 <= B19_FF * amp19;

end Behavioral;

