library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity deteccion is
    Port ( 	CLK : in  STD_LOGIC;                                    	-- Tiene que funcionar a 48000
				notasent : in STD_LOGIC_VECTOR (11 downto 0); 				-- Notas arpa funcionan solo 12 de C a C - F/G
				en : in STD_LOGIC;
				des : out STD_LOGIC_VECTOR (11 downto 0)
				); 
end deteccion;

architecture Behavioral of deteccion is

signal Salint : STD_LOGIC_VECTOR (11 downto 0):= (others=>'0');

begin

Process (CLK)
begin
	if (CLK'event and CLK='1') then
		if (en='0')then
			if	(notasent(11)='1') then Salint(11) <= '0';
			else Salint(11)<='1';
			end if;
		
			if	(notasent(10)='1') then Salint(10) <= '0';
			else Salint(10)<='1';
			end if;
		
			if	(notasent(9)='1') then Salint(9) <= '0';
			else Salint(9)<='1';
			end if;
		
			if	(notasent(8)='1') then Salint(8) <= '0';
			else Salint(8)<='1';
			end if;
		
			if	(notasent(7)='1') then Salint(7) <= '0';
			else Salint(7)<='1';
			end if;
		
			if	(notasent(6)='1') then Salint(6) <= '0';
			else Salint(6)<='1';
			end if;
		
			if	(notasent(5)='1') then Salint(5) <= '0';
			else Salint(5)<='1';
			end if;
		
			if	(notasent(4)='1') then Salint(4) <= '0';
			else Salint(11)<='1';
			end if;
		
			if	(notasent(3)='1') then Salint(3) <= '0';
			else Salint(3)<='1';
			end if;
		
			if	(notasent(2)='1') then Salint(2) <= '0';
			else Salint(2)<='1';
			end if;
		
			if	(notasent(1)='1') then Salint(1) <= '0';
			else Salint(1)<='1';
			end if;
		
			if	(notasent(0)='1') then Salint(0) <= '0';
			else Salint(0)<='1';
			end if;

			
		else Salint <= Salint;
		end if;
	end if;
end process;
		
des <= Salint;		

end Behavioral;



