library IEEE;
use IEEE.STD_LOGIC_1164.all;

package componentes is 

component divisor1 is
	Port ( CLK : in STD_LOGIC;
			 RST : in STD_LOGIC;
			 salida : out STD_LOGIC
			 );
end component;

component divisor2 is
	Port ( CLK : in STD_LOGIC;
			 RST : in STD_LOGIC;
		    salida : out STD_LOGIC);
end component;

component divisor3 is
	Port ( CLK : in STD_LOGIC;
		    RST : in STD_LOGIC;
		    salida : out STD_LOGIC);
end component;
				
component g00_audio_interface IS
	PORT(	LDATA, RDATA	: IN std_logic_vector(23 downto 0); -- parallel external data inputs
			clk, rst, INIT, W_EN : IN std_logic; -- clk should be 24MHz
			pulse_48KHz : OUT std_logic; -- sample sync pulse
			AUD_MCLK : OUT std_logic; -- codec master clock input
			AUD_BCLK : OUT std_logic; -- digital audio bit clock
			AUD_DACDAT : OUT std_logic; -- DAC data lines
			AUD_DACLRCK : OUT std_logic; -- DAC data left/right select
			I2C_SDAT : OUT std_logic; -- serial interface data line
			I2C_SCLK : OUT std_logic  -- serial interface clock
			);
END component;

component LED is
    Port ( entrada : in  STD_LOGIC_VECTOR (4 downto 0);
           salida : out  STD_LOGIC_VECTOR (17 downto 0));
end component;

component fase is
    Port ( 	CLK : in  STD_LOGIC;                                    
				num_nota : in STD_LOGIC_VECTOR (4 downto 0);  
				num_inst : in STD_LOGIC_VECTOR (1 downto 0);
				f1 : out STD_LOGIC_VECTOR (8 downto 0);
				f2 : out STD_LOGIC_VECTOR (8 downto 0);
				f3 : out STD_LOGIC_VECTOR (8 downto 0);
				f4 : out STD_LOGIC_VECTOR (8 downto 0);
				f5 : out STD_LOGIC_VECTOR (8 downto 0);
				f6 : out STD_LOGIC_VECTOR (8 downto 0);
				f7 : out STD_LOGIC_VECTOR (8 downto 0);
				f8 : out STD_LOGIC_VECTOR (8 downto 0);
				f9 : out STD_LOGIC_VECTOR (8 downto 0);
				f10 : out STD_LOGIC_VECTOR (8 downto 0);
				f11 : out STD_LOGIC_VECTOR (8 downto 0);
				f12 : out STD_LOGIC_VECTOR (8 downto 0);
				f13 : out STD_LOGIC_VECTOR (8 downto 0);
				f14 : out STD_LOGIC_VECTOR (8 downto 0);
				f15 : out STD_LOGIC_VECTOR (8 downto 0);
				f16 : out STD_LOGIC_VECTOR (8 downto 0);
				f17 : out STD_LOGIC_VECTOR (8 downto 0);
				f18 : out STD_LOGIC_VECTOR (8 downto 0);
				f19 : out STD_LOGIC_VECTOR (8 downto 0));
end component;

component amplitud is
    Port ( 	CLK : in  STD_LOGIC;                                 
				num_nota : in STD_LOGIC_VECTOR (4 downto 0);  
				num_inst : in STD_LOGIC_VECTOR (1 downto 0);
				af : out STD_LOGIC_VECTOR (7 downto 0);
				a1 : out STD_LOGIC_VECTOR (7 downto 0);								
				a2 : out STD_LOGIC_VECTOR (7 downto 0);								
				a3 : out STD_LOGIC_VECTOR (7 downto 0);								
				a4 : out STD_LOGIC_VECTOR (7 downto 0);								
				a5 : out STD_LOGIC_VECTOR (7 downto 0);								
				a6 : out STD_LOGIC_VECTOR (7 downto 0);								
				a7 : out STD_LOGIC_VECTOR (7 downto 0);								
				a8 : out STD_LOGIC_VECTOR (7 downto 0);								
				a9 : out STD_LOGIC_VECTOR (7 downto 0);								
				a10 : out STD_LOGIC_VECTOR (7 downto 0);								
				a11 : out STD_LOGIC_VECTOR (7 downto 0);								
				a12 : out STD_LOGIC_VECTOR (7 downto 0);								
				a13 : out STD_LOGIC_VECTOR (7 downto 0);								
				a14 : out STD_LOGIC_VECTOR (7 downto 0);								
				a15 : out STD_LOGIC_VECTOR (7 downto 0);								
				a16 : out STD_LOGIC_VECTOR (7 downto 0);								
				a17 : out STD_LOGIC_VECTOR (7 downto 0);								
				a18 : out STD_LOGIC_VECTOR (7 downto 0);								
				a19 : out STD_LOGIC_VECTOR (7 downto 0));
end component;

component control is
    Port ( 	CLK : in STD_LOGIC;                                    	
				RST : in STD_LOGIC;
				cont : out STD_LOGIC_VECTOR (4 downto 0));
end component;

component incrementos is
    Port ( 	CLK : in  STD_LOGIC;                                    
				num_nota : in STD_LOGIC_VECTOR (4 downto 0);  
				num_inst : in STD_LOGIC_VECTOR (1 downto 0);
				Sale : out integer;
				Sal : out STD_LOGIC_VECTOR (17 downto 0)); 
end component;

component arm is
    Port ( 	CLK : in  STD_LOGIC;                                    
				num_nota : in STD_LOGIC_VECTOR (4 downto 0);  
				num_inst : in STD_LOGIC_VECTOR (1 downto 0);
				RST : in STD_LOGIC;
				INCe : in integer;
				INC : in STD_LOGIC_VECTOR (17 downto 0);
				Bf : out STD_LOGIC_VECTOR (19 downto 0);
				B1 : out STD_LOGIC_VECTOR (19 downto 0);
				B2 : out STD_LOGIC_VECTOR (19 downto 0);
				B3 : out STD_LOGIC_VECTOR (19 downto 0);
				B4 : out STD_LOGIC_VECTOR (19 downto 0);
				B5 : out STD_LOGIC_VECTOR (19 downto 0);
				B6 : out STD_LOGIC_VECTOR (19 downto 0);
				B7 : out STD_LOGIC_VECTOR (19 downto 0);
				B8 : out STD_LOGIC_VECTOR (19 downto 0);
				B9 : out STD_LOGIC_VECTOR (19 downto 0);
				B10 : out STD_LOGIC_VECTOR (19 downto 0);
				B11 : out STD_LOGIC_VECTOR (19 downto 0);
				B12 : out STD_LOGIC_VECTOR (19 downto 0);
				B13 : out STD_LOGIC_VECTOR (19 downto 0);
				B14 : out STD_LOGIC_VECTOR (19 downto 0);
				B15 : out STD_LOGIC_VECTOR (19 downto 0);
				B16 : out STD_LOGIC_VECTOR (19 downto 0);
				B17 : out STD_LOGIC_VECTOR (19 downto 0);
				B18 : out STD_LOGIC_VECTOR (19 downto 0);
				B19 : out STD_LOGIC_VECTOR (19 downto 0));
end component;

component acum is
    Port ( 	CLK : in  STD_LOGIC;                                    
				RST : in STD_LOGIC;
				Bf_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B1_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B2_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B3_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B4_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B5_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B6_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B7_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B8_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B9_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B10_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B11_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B12_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B13_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B14_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B15_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B16_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B17_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B18_1 : in STD_LOGIC_VECTOR (19 downto 0);
				B19_1 : in STD_LOGIC_VECTOR (19 downto 0);
				Bf : out STD_LOGIC_VECTOR (19 downto 0);
				B1 : out STD_LOGIC_VECTOR (19 downto 0);
				B2 : out STD_LOGIC_VECTOR (19 downto 0);
				B3 : out STD_LOGIC_VECTOR (19 downto 0);
				B4 : out STD_LOGIC_VECTOR (19 downto 0);
				B5 : out STD_LOGIC_VECTOR (19 downto 0);
				B6 : out STD_LOGIC_VECTOR (19 downto 0);
				B7 : out STD_LOGIC_VECTOR (19 downto 0);
				B8 : out STD_LOGIC_VECTOR (19 downto 0);
				B9 : out STD_LOGIC_VECTOR (19 downto 0);
				B10 : out STD_LOGIC_VECTOR (19 downto 0);
				B11 : out STD_LOGIC_VECTOR (19 downto 0);
				B12 : out STD_LOGIC_VECTOR (19 downto 0);
				B13 : out STD_LOGIC_VECTOR (19 downto 0);
				B14 : out STD_LOGIC_VECTOR (19 downto 0);
				B15 : out STD_LOGIC_VECTOR (19 downto 0);
				B16 : out STD_LOGIC_VECTOR (19 downto 0);
				B17 : out STD_LOGIC_VECTOR (19 downto 0);
				B18 : out STD_LOGIC_VECTOR (19 downto 0);
				B19 : out STD_LOGIC_VECTOR (19 downto 0)	
				);
end component;

component sumfas is
    Port ( 	fase1 : in STD_LOGIC_VECTOR (8 downto 0);
				fase2 : in STD_LOGIC_VECTOR (8 downto 0);
				fase3 : in STD_LOGIC_VECTOR (8 downto 0);
				fase4 : in STD_LOGIC_VECTOR (8 downto 0);
				fase5 : in STD_LOGIC_VECTOR (8 downto 0);
				fase6 : in STD_LOGIC_VECTOR (8 downto 0);
				fase7 : in STD_LOGIC_VECTOR (8 downto 0);
				fase8 : in STD_LOGIC_VECTOR (8 downto 0);
				fase9 : in STD_LOGIC_VECTOR (8 downto 0);
				fase10 : in STD_LOGIC_VECTOR (8 downto 0);
				fase11 : in STD_LOGIC_VECTOR (8 downto 0);
				fase12 : in STD_LOGIC_VECTOR (8 downto 0);
				fase13 : in STD_LOGIC_VECTOR (8 downto 0);
				fase14 : in STD_LOGIC_VECTOR (8 downto 0);
				fase15 : in STD_LOGIC_VECTOR (8 downto 0);
				fase16 : in STD_LOGIC_VECTOR (8 downto 0);
				fase17 : in STD_LOGIC_VECTOR (8 downto 0);
				fase18 : in STD_LOGIC_VECTOR (8 downto 0);
				fase19 : in STD_LOGIC_VECTOR (8 downto 0);
				Bf_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B1_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B2_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B3_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B4_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B5_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B6_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B7_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B8_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B9_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B10_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B11_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B12_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B13_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B14_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B15_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B16_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B17_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B18_2 : in STD_LOGIC_VECTOR (19 downto 0);
				B19_2 : in STD_LOGIC_VECTOR (19 downto 0);	
				Bf_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B1_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B2_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B3_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B4_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B5_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B6_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B7_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B8_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B9_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B10_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B11_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B12_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B13_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B14_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B15_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B16_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B17_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B18_3 : out STD_LOGIC_VECTOR (8 downto 0);
				B19_3 : out STD_LOGIC_VECTOR (8 downto 0)
				);
end component;

component FF1 is
    Port ( 	CLK : in  STD_LOGIC;                                    
				Bf_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B1_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B2_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B3_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B4_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B5_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B6_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B7_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B8_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B9_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B10_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B11_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B12_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B13_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B14_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B15_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B16_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B17_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B18_3 : in STD_LOGIC_VECTOR (8 downto 0);
				B19_3 : in STD_LOGIC_VECTOR (8 downto 0);
				Bf : out STD_LOGIC_VECTOR (8 downto 0);
				B1 : out STD_LOGIC_VECTOR (8 downto 0);
				B2 : out STD_LOGIC_VECTOR (8 downto 0);
				B3 : out STD_LOGIC_VECTOR (8 downto 0);
				B4 : out STD_LOGIC_VECTOR (8 downto 0);
				B5 : out STD_LOGIC_VECTOR (8 downto 0);
				B6 : out STD_LOGIC_VECTOR (8 downto 0);
				B7 : out STD_LOGIC_VECTOR (8 downto 0);
				B8 : out STD_LOGIC_VECTOR (8 downto 0);
				B9 : out STD_LOGIC_VECTOR (8 downto 0);
				B10 : out STD_LOGIC_VECTOR (8 downto 0);
				B11 : out STD_LOGIC_VECTOR (8 downto 0);
				B12 : out STD_LOGIC_VECTOR (8 downto 0);
				B13 : out STD_LOGIC_VECTOR (8 downto 0);
				B14 : out STD_LOGIC_VECTOR (8 downto 0);
				B15 : out STD_LOGIC_VECTOR (8 downto 0);
				B16 : out STD_LOGIC_VECTOR (8 downto 0);
				B17 : out STD_LOGIC_VECTOR (8 downto 0);
				B18 : out STD_LOGIC_VECTOR (8 downto 0);
				B19 : out STD_LOGIC_VECTOR (8 downto 0)
				);
end component;

component mux1 is
    Port ( 	CLK : in  STD_LOGIC;                                    
				Qint : in STD_LOGIC_VECTOR (4 downto 0);
				Ff : in STD_LOGIC_VECTOR (8 downto 0);
				F1 : in STD_LOGIC_VECTOR (8 downto 0);
				F2 : in STD_LOGIC_VECTOR (8 downto 0);
				F3 : in STD_LOGIC_VECTOR (8 downto 0);
				F4 : in STD_LOGIC_VECTOR (8 downto 0);
				F5 : in STD_LOGIC_VECTOR (8 downto 0);
				F6 : in STD_LOGIC_VECTOR (8 downto 0);
				F7 : in STD_LOGIC_VECTOR (8 downto 0);
				F8 : in STD_LOGIC_VECTOR (8 downto 0);
				F9 : in STD_LOGIC_VECTOR (8 downto 0);
				F10 : in STD_LOGIC_VECTOR (8 downto 0);
				F11 : in STD_LOGIC_VECTOR (8 downto 0);
				F12 : in STD_LOGIC_VECTOR (8 downto 0);
				F13 : in STD_LOGIC_VECTOR (8 downto 0);
				F14 : in STD_LOGIC_VECTOR (8 downto 0);
				F15 : in STD_LOGIC_VECTOR (8 downto 0);
				F16 : in STD_LOGIC_VECTOR (8 downto 0);
				F17 : in STD_LOGIC_VECTOR (8 downto 0);
				F18 : in STD_LOGIC_VECTOR (8 downto 0);
				F19 : in STD_LOGIC_VECTOR (8 downto 0);
				sal : out STD_LOGIC_VECTOR (8 downto 0)
				);
end component;

component sen is
    Port ( dir_mem : in STD_LOGIC_VECTOR (8 downto 0);
			  sal : out integer
			  );
end component;

component DMUX is
    Port ( 	CLK : in  STD_LOGIC;                                    
				Qint : in STD_LOGIC_VECTOR (4 downto 0);
				sen : in integer;
				Bf : out STD_LOGIC_VECTOR (7 downto 0);
				B1 : out STD_LOGIC_VECTOR (7 downto 0);
				B2 : out STD_LOGIC_VECTOR (7 downto 0);
				B3 : out STD_LOGIC_VECTOR (7 downto 0);
				B4 : out STD_LOGIC_VECTOR (7 downto 0);
				B5 : out STD_LOGIC_VECTOR (7 downto 0);
				B6 : out STD_LOGIC_VECTOR (7 downto 0);
				B7 : out STD_LOGIC_VECTOR (7 downto 0);
				B8 : out STD_LOGIC_VECTOR (7 downto 0);
				B9 : out STD_LOGIC_VECTOR (7 downto 0);
				B10 : out STD_LOGIC_VECTOR (7 downto 0);
				B11 : out STD_LOGIC_VECTOR (7 downto 0);
				B12 : out STD_LOGIC_VECTOR (7 downto 0);
				B13 : out STD_LOGIC_VECTOR (7 downto 0);
				B14 : out STD_LOGIC_VECTOR (7 downto 0);
				B15 : out STD_LOGIC_VECTOR (7 downto 0);
				B16 : out STD_LOGIC_VECTOR (7 downto 0);
				B17 : out STD_LOGIC_VECTOR (7 downto 0);
				B18 : out STD_LOGIC_VECTOR (7 downto 0);
				B19 : out STD_LOGIC_VECTOR (7 downto 0)
				);
end component;

component FF2 is
    Port ( 	CLK : in  STD_LOGIC;                                    
				Qint : in STD_LOGIC_VECTOR (4 downto 0);
				Bf_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B1_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B2_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B3_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B4_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B5_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B6_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B7_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B8_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B9_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B10_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B11_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B12_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B13_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B14_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B15_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B16_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B17_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B18_5 : in STD_LOGIC_VECTOR (7 downto 0);
				B19_5 : in STD_LOGIC_VECTOR (7 downto 0);
				Bf : out STD_LOGIC_VECTOR (7 downto 0);
				B1 : out STD_LOGIC_VECTOR (7 downto 0);
				B2 : out STD_LOGIC_VECTOR (7 downto 0);
				B3 : out STD_LOGIC_VECTOR (7 downto 0);
				B4 : out STD_LOGIC_VECTOR (7 downto 0);
				B5 : out STD_LOGIC_VECTOR (7 downto 0);
				B6 : out STD_LOGIC_VECTOR (7 downto 0);
				B7 : out STD_LOGIC_VECTOR (7 downto 0);
				B8 : out STD_LOGIC_VECTOR (7 downto 0);
				B9 : out STD_LOGIC_VECTOR (7 downto 0);
				B10 : out STD_LOGIC_VECTOR (7 downto 0);
				B11 : out STD_LOGIC_VECTOR (7 downto 0);
				B12 : out STD_LOGIC_VECTOR (7 downto 0);
				B13 : out STD_LOGIC_VECTOR (7 downto 0);
				B14 : out STD_LOGIC_VECTOR (7 downto 0);
				B15 : out STD_LOGIC_VECTOR (7 downto 0);
				B16 : out STD_LOGIC_VECTOR (7 downto 0);
				B17 : out STD_LOGIC_VECTOR (7 downto 0);
				B18 : out STD_LOGIC_VECTOR (7 downto 0);
				B19 : out STD_LOGIC_VECTOR (7 downto 0)
				);
end component;

component mult is
    Port ( 	ampfund : in STD_LOGIC_VECTOR (7 downto 0);
				amp1 : in STD_LOGIC_VECTOR (7 downto 0);
				amp2 : in STD_LOGIC_VECTOR (7 downto 0);
				amp3 : in STD_LOGIC_VECTOR (7 downto 0);
				amp4 : in STD_LOGIC_VECTOR (7 downto 0);
				amp5 : in STD_LOGIC_VECTOR (7 downto 0);
				amp6 : in STD_LOGIC_VECTOR (7 downto 0);
				amp7 : in STD_LOGIC_VECTOR (7 downto 0);
				amp8 : in STD_LOGIC_VECTOR (7 downto 0);
				amp9 : in STD_LOGIC_VECTOR (7 downto 0);
				amp10 : in STD_LOGIC_VECTOR (7 downto 0);
				amp11 : in STD_LOGIC_VECTOR (7 downto 0);
				amp12 : in STD_LOGIC_VECTOR (7 downto 0);
				amp13 : in STD_LOGIC_VECTOR (7 downto 0);
				amp14 : in STD_LOGIC_VECTOR (7 downto 0);
				amp15 : in STD_LOGIC_VECTOR (7 downto 0);
				amp16 : in STD_LOGIC_VECTOR (7 downto 0);
				amp17 : in STD_LOGIC_VECTOR (7 downto 0);
				amp18 : in STD_LOGIC_VECTOR (7 downto 0);
				amp19 : in STD_LOGIC_VECTOR (7 downto 0);
				Bf_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B1_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B2_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B3_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B4_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B5_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B6_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B7_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B8_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B9_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B10_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B11_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B12_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B13_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B14_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B15_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B16_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B17_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B18_FF : in STD_LOGIC_VECTOR (7 downto 0);
				B19_FF : in STD_LOGIC_VECTOR (7 downto 0);
				Bf_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B1_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B2_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B3_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B4_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B5_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B6_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B7_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B8_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B9_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B10_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B11_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B12_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B13_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B14_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B15_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B16_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B17_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B18_6 : out STD_LOGIC_VECTOR (15 downto 0);
				B19_6 : out STD_LOGIC_VECTOR (15 downto 0)
				);
end component;

component offset is
    Port ( 	ampfund : in STD_LOGIC_VECTOR (7 downto 0);
				amp1 : in STD_LOGIC_VECTOR (7 downto 0);
				amp2 : in STD_LOGIC_VECTOR (7 downto 0);
				amp3 : in STD_LOGIC_VECTOR (7 downto 0);
				amp4 : in STD_LOGIC_VECTOR (7 downto 0);
				amp5 : in STD_LOGIC_VECTOR (7 downto 0);
				amp6 : in STD_LOGIC_VECTOR (7 downto 0);
				amp7 : in STD_LOGIC_VECTOR (7 downto 0);
				amp8 : in STD_LOGIC_VECTOR (7 downto 0);
				amp9 : in STD_LOGIC_VECTOR (7 downto 0);
				amp10 : in STD_LOGIC_VECTOR (7 downto 0);
				amp11 : in STD_LOGIC_VECTOR (7 downto 0);
				amp12 : in STD_LOGIC_VECTOR (7 downto 0);
				amp13 : in STD_LOGIC_VECTOR (7 downto 0);
				amp14 : in STD_LOGIC_VECTOR (7 downto 0);
				amp15 : in STD_LOGIC_VECTOR (7 downto 0);
				amp16 : in STD_LOGIC_VECTOR (7 downto 0);
				amp17 : in STD_LOGIC_VECTOR (7 downto 0);
				amp18 : in STD_LOGIC_VECTOR (7 downto 0);
				amp19 : in STD_LOGIC_VECTOR (7 downto 0);
				Bf_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B1_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B2_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B3_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B4_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B5_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B6_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B7_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B8_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B9_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B10_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B11_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B12_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B13_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B14_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B15_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B16_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B17_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B18_6 : in STD_LOGIC_VECTOR (15 downto 0);
				B19_6 : in STD_LOGIC_VECTOR (15 downto 0);
				Bf_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B1_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B2_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B3_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B4_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B5_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B6_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B7_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B8_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B9_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B10_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B11_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B12_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B13_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B14_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B15_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B16_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B17_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B18_7 : out STD_LOGIC_VECTOR (15 downto 0);
				B19_7 : out STD_LOGIC_VECTOR (15 downto 0)
				);
end component;

component suma is
    Port ( 	Bf_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B1_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B2_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B3_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B4_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B5_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B6_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B7_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B8_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B9_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B10_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B11_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B12_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B13_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B14_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B15_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B16_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B17_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B18_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B19_7 : in STD_LOGIC_VECTOR (15 downto 0);
				Sal : out STD_LOGIC_VECTOR (19 downto 0)
				);
end component;

component ajuste is
    Port ( 	Ent : in STD_LOGIC_VECTOR (19 downto 0);
				Sal1 : out STD_LOGIC_VECTOR (23 downto 0);
				Sal2 : out STD_LOGIC_VECTOR (23 downto 0)
				);
end component;

component arp is
    Port ( 	CLK : in  STD_LOGIC;                                    	
				notas : in STD_LOGIC_VECTOR (11 downto 0); 					
				des : in STD_LOGIC_VECTOR (11 downto 0);						
				Sal : out STD_LOGIC_VECTOR (11 downto 0)						
				); 
end component;

component calc_notas is
    Port ( 	CLK : in  STD_LOGIC;                                    	
				notasent : in STD_LOGIC_VECTOR (11 downto 0); 				
				nota1 : out STD_LOGIC_VECTOR (4 downto 0);
				nota2 : out STD_LOGIC_VECTOR (4 downto 0)
				); 
end component;

component sumfin is
    Port ( 	Ent1 : in STD_LOGIC_VECTOR (23 downto 0);
				Ent1_2 : in STD_LOGIC_VECTOR (23 downto 0);
				Ent2 : in STD_LOGIC_VECTOR (23 downto 0);
				Ent2_2 : in STD_LOGIC_VECTOR (23 downto 0);
				Sal1 : out STD_LOGIC_VECTOR (23 downto 0);
				Sal2 : out STD_LOGIC_VECTOR (23 downto 0)
				);
end component;

component seleccion is
    Port ( 	sel : in std_logic;
			clk : in std_logic;
			notas_arp :in STD_LOGIC_VECTOR (11 downto 0); 
			notas_int :in STD_LOGIC_VECTOR (11 downto 0); 
			notas_sel: out STD_LOGIC_VECTOR (11 downto 0)
				); 
end component;

component deteccion is
    Port ( 	CLK : in  STD_LOGIC;                                    	
				notasent : in STD_LOGIC_VECTOR (11 downto 0); 				
				en : in STD_LOGIC;
				des : out STD_LOGIC_VECTOR (11 downto 0)
				); 
end component;

component invertir is
    Port ( 	CLK : in  STD_LOGIC;                                    	
				notas : in STD_LOGIC_VECTOR (11 downto 0); 					
				notas_inv : out STD_LOGIC_VECTOR (11 downto 0)						
				); 
end component;

component LED2 is
    Port ( notas_sel : in  STD_LOGIC_VECTOR (11 downto 0);
           leds : out  STD_LOGIC_VECTOR (11 downto 0));
end component;

component LED3 is
    Port ( 	INIT : IN std_logic; 
			CLK : IN std_logic; 
           W_EN : IN std_logic;
           RST : in STD_LOGIC;
           sel : IN std_logic;									--modo
           num_inst : in STD_LOGIC_VECTOR (1 downto 0);
			LED_config : out STD_LOGIC_VECTOR (2 downto 0);
			LED_modo : out std_logic;	
			LED_inst : out STD_LOGIC_VECTOR (1 downto 0));
end component;

end componentes;

