library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ajuste is
    Port ( 	Ent : in STD_LOGIC_VECTOR (19 downto 0);
				Sal1 : out STD_LOGIC_VECTOR (23 downto 0);
				Sal2 : out STD_LOGIC_VECTOR (23 downto 0)
				);
end ajuste;

architecture Behavioral of ajuste is

begin

Sal1 <= "0" & Ent & "000";     	-- Dependiendo de los 0 que tengamos delante y detras variara el volumen
Sal2 <= "0" & Ent & "000";	  		-- otro canal

end Behavioral;

