library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity control is
    Port ( 	CLK : in STD_LOGIC;                                    	-- Tiene que funcionar a 48000*21= 1008000
				RST : in STD_LOGIC;
				cont : out STD_LOGIC_VECTOR (4 downto 0)						
				);
end control;

architecture Behavioral of control is

signal Qint: STD_LOGIC_VECTOR (4 downto 0):= (others=>'0');

begin

Process (CLK)
begin
	if (CLK'event and CLK='1') then
		if (RST='1') then
			Qint <= "00000";
		else
			if Qint = 20 then Qint <= "00000";
			else Qint <= Qint+1;														-- Qint seņales control MUX
			end if;
		end if;				
	end if;
end process;	

cont <= Qint;

end Behavioral;

