library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity suma is
    Port ( 	Bf_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B1_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B2_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B3_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B4_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B5_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B6_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B7_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B8_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B9_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B10_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B11_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B12_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B13_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B14_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B15_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B16_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B17_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B18_7 : in STD_LOGIC_VECTOR (15 downto 0);
				B19_7 : in STD_LOGIC_VECTOR (15 downto 0);
				Sal : out STD_LOGIC_VECTOR (19 downto 0)
				);
end suma;

architecture Behavioral of suma is

begin

Sal <= "0000" & Bf_7 + B1_7 + B2_7 + B3_7 + B4_7 + B5_7 + B6_7 + B7_7 + B8_7 + B9_7 + B10_7 + B11_7 + B12_7 + B13_7 
		 + B14_7 + B15_7 + B16_7 + B17_7 + B18_7 + B19_7; 

end Behavioral;

