library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux1 is
    Port ( 	CLK : in  STD_LOGIC;                                    -- Tiene que funcionar a 48000 * 21
				Qint : in STD_LOGIC_VECTOR (4 downto 0);
				Ff : in STD_LOGIC_VECTOR (8 downto 0);
				F1 : in STD_LOGIC_VECTOR (8 downto 0);
				F2 : in STD_LOGIC_VECTOR (8 downto 0);
				F3 : in STD_LOGIC_VECTOR (8 downto 0);
				F4 : in STD_LOGIC_VECTOR (8 downto 0);
				F5 : in STD_LOGIC_VECTOR (8 downto 0);
				F6 : in STD_LOGIC_VECTOR (8 downto 0);
				F7 : in STD_LOGIC_VECTOR (8 downto 0);
				F8 : in STD_LOGIC_VECTOR (8 downto 0);
				F9 : in STD_LOGIC_VECTOR (8 downto 0);
				F10 : in STD_LOGIC_VECTOR (8 downto 0);
				F11 : in STD_LOGIC_VECTOR (8 downto 0);
				F12 : in STD_LOGIC_VECTOR (8 downto 0);
				F13 : in STD_LOGIC_VECTOR (8 downto 0);
				F14 : in STD_LOGIC_VECTOR (8 downto 0);
				F15 : in STD_LOGIC_VECTOR (8 downto 0);
				F16 : in STD_LOGIC_VECTOR (8 downto 0);
				F17 : in STD_LOGIC_VECTOR (8 downto 0);
				F18 : in STD_LOGIC_VECTOR (8 downto 0);
				F19 : in STD_LOGIC_VECTOR (8 downto 0);
				sal : out STD_LOGIC_VECTOR (8 downto 0)
				);
end mux1;

architecture Behavioral of mux1 is

signal dir_mem : STD_LOGIC_VECTOR (8 downto 0):= (others=>'0');

begin

Process (CLK)										
	begin	
		if (CLK'event and CLK='1') then		
			if (Qint="00000") then dir_mem <= Ff;
			elsif (Qint="00001") then dir_mem <= F1;
			elsif (Qint="00010") then dir_mem <= F2;
			elsif (Qint="00011") then dir_mem <= F3;
			elsif (Qint="00100") then dir_mem <= F4;
			elsif (Qint="00101") then dir_mem <= F5;
			elsif (Qint="00110") then dir_mem <= F6;
			elsif (Qint="00111") then dir_mem <= F7;
			elsif (Qint="01000") then dir_mem <= F8;
			elsif (Qint="01001") then dir_mem <= F9;
			elsif (Qint="01010") then dir_mem <= F10;
			elsif (Qint="01011") then dir_mem <= F11;
			elsif (Qint="01100") then dir_mem <= F12;
			elsif (Qint="01101") then dir_mem <= F13;
			elsif (Qint="01110") then dir_mem <= F14;
			elsif (Qint="01111") then dir_mem <= F15;
			elsif (Qint="10000") then dir_mem <= F16;
			elsif (Qint="10001") then dir_mem <= F17;
			elsif (Qint="10010") then dir_mem <= F18;
			elsif (Qint="10011") then dir_mem <= F19;
			elsif (Qint="10100") then dir_mem <= F19;
			end if;		
		end if;
end process;

sal <= dir_mem;

end Behavioral;

