library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity invertir is
    Port ( 	CLK : in  STD_LOGIC;                                    	-- Tiene que funcionar a 48000
				notas : in STD_LOGIC_VECTOR (11 downto 0); 					-- Notas arpa
				notas_inv : out STD_LOGIC_VECTOR (11 downto 0)						
				); 
end invertir;

architecture Behavioral of invertir is

signal Salint : STD_LOGIC_VECTOR (11 downto 0):= (others=>'0');

begin

Process (CLK)
begin
	if (CLK'event and CLK='1') then
		if	(notas(11)='0') then Salint(11) <= '1';
		else Salint(11)<='0';
		end if;

		if	(notas(10)='0') then Salint(10) <='1';
		else Salint(10)<='0';
		end if;
		
		if	(notas(9)='0') then Salint(9) <= '1';
		else Salint(9)<='0';
		end if;
		
		if	(notas(8)='0') then Salint(8) <= '1';
		else Salint(8)<='0';
		end if;
		
		if	(notas(7)='0') then Salint(7) <= '1';
		else Salint(7)<='0';
		end if;
		
		if	(notas(6)='0') then Salint(6) <= '1';
		else Salint(6)<='0';
		end if;
		
		if	(notas(5)='0') then Salint(5) <= '1';
		else Salint(5)<='0';
		end if;
		
		if	(notas(4)='0') then Salint(4) <= '1';
		else Salint(4)<='0';
		end if;
		
		if	(notas(3)='0') then Salint(3) <= '1';
		else Salint(3)<='0';
		end if;
		
		if	(notas(2)='0') then Salint(2) <= '1';
		else Salint(2)<='0';
		end if;
		
		if	(notas(1)='0') then Salint(1) <= '1';
		else Salint(1)<='0';
		end if;
		
		if	(notas(0)='0') then Salint(0) <= '1';
		else Salint(0)<='0';
		end if;
				

	end if;
end process;
		
notas_inv <= Salint;		

end Behavioral;

