library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seleccion is
    Port ( 	sel : in std_logic;
			clk : in std_logic;
			notas_arp :in STD_LOGIC_VECTOR (11 downto 0); 
			notas_int :in STD_LOGIC_VECTOR (11 downto 0); -- notas interruptor
			notas_sel: out STD_LOGIC_VECTOR (11 downto 0)
				); 
end seleccion;

architecture Behavioral of seleccion is

signal inter : STD_LOGIC_VECTOR (11 downto 0); 

begin
				  
Process (CLK)
begin
	if (CLK'event and CLK='1') then
		if (sel='1') then inter <= notas_arp;
		else inter <= notas_int;
		end if;
	end if;
end process;

notas_sel <= inter;

end Behavioral;
