In this Ph. D. thesis is presented the design and implementation of integer-pel and 
fractional-pel motion estimation VLSI architectures, for the motion-compensation 
prediction stage of the H.264/AVC video-coding standard. The proposed architectures are 
pipeline-parallel processing structures with high data-path efficiency and optimal memory 
management. They make use of the full-search block-matching algorithm to fulfil the 
standard requirements like variable block size and quarter-pel resolution with maximum 
quality. The motion estimators blend the state-of-the-art architectures characteristics with 
new hardware schemes and algorithms for the luma video component coding process. The 
considered architectures were designed as hardware acceleration co-processors for 32-bit 
processors. They have been simulated and synthesized for Virtex-4 Xilinx FPGA using 
VHDL hardware description language.