[EN] In the Ghiribaldi et al. [2013] paper, a complete self-testing and self configuring NoC infrastructure for cost-effective MPSoCs was presented in order to make NoC architecture tolerant to faults. To overcome the ...
Tornero, Rafael; Orduña Huertas, Juan Manuel; Mejia, Andres; Flich Cardo, José; Duato Marín, José Francisco(Springer Verlag (Germany), 2011-06)
Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the ...
[EN] Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and
configuration strategy however implies two opposite requirements. One one hand, a fast and scalable ...
Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco(Elsevier, 2011-11)
[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we ...
Flich Cardo, José; Skeie, . Tor; Mejia, Andres; Lysne, . Olav; López Rodríguez, Pedro Juan; Robles Martínez, Antonio; Duato Marín, José Francisco; Koibuchi, . Michihiro; Rokicki, . Tomas; Sancho, . Jose Carlos(Institute of Electrical and Electronics Engineers (IEEE), 2012)
Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing algorithms, which make no assumption about the ...
Russo, Davide(Universitat Politècnica de València, 2020-09-18)
[EN] In this work, we adapt a reconfigurable computer system based on FPGA
technologies to OpenCL programming environments. The reconfigurable system
is part of a compute prototype of the MANGO European project that ...
Escudero-Sahuquillo, Jesús; Garcia Garcia, Pedro-Javier; Quiles Flor, Francisco Jose; Flich Cardo, José; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2013-10)
As parallel computing systems increase in size, the interconnection network is becoming a critical subsystem. The current trend in network design is to use as few components as possible to interconnect the end nodes, thereby ...
Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José(Institution of Engineering and Technology (IET), 2013-03)
[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco(Elsevier, 2011-05)
[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Rodrigo Mocholí, Samuel(Universitat Politècnica de València, 2010-11-29)
Arquitecturas de múltiples núcleos como multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) actuales se basan en la eficacia de las redes dentro del chip (NoC) para la comunicación ...
Escudero, Jesús; García García, Pedro Javier; Quiles Flor, Francisco Jose; Flich Cardo, José; Duato Marín, José Francisco(Wiley-Blackwell, 2011)
The fat-tree is one of the most common topologies among the interconnection networks of the systems currently used for high-performance parallel computing. Among other advantages, fat-trees allow the use of simple but very ...
Rodrigo Mocholí, Samuel; Flich Cardo, José; Roca Pérez, Antoni; Medardoni, Simone; Bertozzi, Davide; Camacho Villanueva, Jesús; Silla Jiménez, Federico; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2011-04)
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...
Catalán Gallach, Izan(Universitat Politècnica de València, 2020-09-28)
[ES] En este Trabajo Final de Máster se va a desarrollar el soporte para el uso de sistemas
basados en FPGA en el proceso de tratamiento y filtrado de imágenes para aplicaciones
médicas.
En el TFM se utilizan las librerías ...
Picornell Sanjuan, Tomás(Universitat Politècnica de València, 2015-07-31)
[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de
orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable
y permite tanto la instanciación de un número variable ...
Guaita Masiá, Francisco(Universitat Politècnica de València, 2015-07-31)
[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de
orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable
y permite tanto la instanciación de un número variable ...
Lozano Torres, Raúl(Universitat Politècnica de València, 2015-07-31)
[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de
orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable
y permite tanto la instanciación de un número variable ...
Tamarit Camarero, Cecilio César(Universitat Politècnica de València, 2020-09-28)
[ES] Dada la actual necesidad de innovación a nivel arquitectural, es necesario contar con herramientas y metodologías eficientes para validar y evaluar nuevos diseños. En el ámbito de este TFM se ha diseñado e implementado ...
Andreu Cerezo, Pablo(Universitat Politècnica de València, 2020-07-30)
[EN] Artificial intelligence aims to solve much of the problems of the contemporary society that we live in. But, in order for it to be ever so prevalent, the development of efficient inference-specific chips is needed, ...
Juvaa, Boldbaatar(Universitat Politècnica de València, 2015-09-29)
[EN] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads ...