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Browsing by Author "Flich Cardo, José"

Now showing items 1-20 of 78

A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs"

Bishnoi, Rimpy; Laxmi, Vijay; Gaur, Manoj Singh; Flich Cardo, José; Trivino, Francisco (Association for Computing Machinery (ACM), 2015-01)

[EN] In the Ghiribaldi et al. [2013] paper, a complete self-testing and self configuring NoC infrastructure for cost-effective MPSoCs was presented in order to make NoC architecture tolerant to faults. To overcome the ...
A communication-driven routing technique for application-specific NoCs

Tornero, Rafael; Orduña Huertas, Juan Manuel; Mejia, Andres; Flich Cardo, José; Duato Marín, José Francisco (Springer Verlag (Germany), 2011-06)

Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the ...
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs

Ghiribaldi, Alberto; Ludovici, Daniele; Triviño, Francisco; Strano, Alessandro; Flich Cardo, José; Sanchez Garcia, Jose Luis; Alfaro, Francisco; Favalli, Michelle; Bertozzi, Davide (Association for Computing Machinery (ACM), 2013-06)

[EN] Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. One one hand, a fast and scalable ...
A low-latency modular switch for CMP systems

Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-11)

[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we ...
A survey and evaluation of topology-agnostic deterministic routing algorithms

Flich Cardo, José; Skeie, . Tor; Mejia, Andres; Lysne, . Olav; López Rodríguez, Pedro Juan; Robles Martínez, Antonio; Duato Marín, José Francisco; Koibuchi, . Michihiro; Rokicki, . Tomas; Sancho, . Jose Carlos (Institute of Electrical and Electronics Engineers (IEEE), 2012)

Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing algorithms, which make no assumption about the ...
Adaptation of High Performance and High Capacity Reconfigurable Systems to OpenCL Programming Environments

Russo, Davide (Universitat Politècnica de València, 2020-09-18)

[EN] In this work, we adapt a reconfigurable computer system based on FPGA technologies to OpenCL programming environments. The reconfigurable system is part of a compute prototype of the MANGO European project that ...
An effective and feasible congestion management technique for high-performance MINs with tag-based distributed routing

Escudero-Sahuquillo, Jesús; Garcia Garcia, Pedro-Javier; Quiles Flor, Francisco Jose; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2013-10)

As parallel computing systems increase in size, the interconnection network is becoming a critical subsystem. The current trend in network design is to use as few components as possible to interconnect the end nodes, thereby ...
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Built-in fast gather control network for efficient support of coherence protocols

Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José (Institution of Engineering and Technology (IET), 2013-03)

[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
Characterizing the impact of process variation on 45 nm NoC-based CMPs

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-05)

[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Conflict-Free Networks on Chip for Real Time Systems

Picornell Sanjuan, Tomás (Universitat Politècnica de València, 2021-11-22)

[ES] La constante necesidad de un mayor rendimiento para cumplir con la gran demanda de potencia de cómputo de las nuevas aplicaciones, (ej. sistemas de conducción autónoma), obliga a la industria a apostar por la tecnología ...
Cost Effective Routing Implementations for On-chip Networks

Rodrigo Mocholí, Samuel (Universitat Politècnica de València, 2010-11-29)

Arquitecturas de múltiples núcleos como multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) actuales se basan en la eficacia de las redes dentro del chip (NoC) para la comunicación ...
Cost-effective queue schemes for reducing head-of-line blocking in fat-trees

Escudero, Jesús; García García, Pedro Javier; Quiles Flor, Francisco Jose; Flich Cardo, José; Duato Marín, José Francisco (Wiley-Blackwell, 2011)

The fat-tree is one of the most common topologies among the interconnection networks of the systems currently used for high-performance parallel computing. Among other advantages, fat-trees allow the use of simple but very ...
Cost-efficient on-chip routing implementations for CMP and MPSoC systems

Rodrigo Mocholí, Samuel; Flich Cardo, José; Roca Pérez, Antoni; Medardoni, Simone; Bertozzi, Davide; Camacho Villanueva, Jesús; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-04)

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs

Zoni, Davide; Flich Cardo, José; Fornaciari, William (Institute of Electrical and Electronics Engineers (IEEE), 2016)

[EN] Router's buffer design and management strongly influence energy, area and performance of on-chip networks, hence it is crucial to encompass all of these aspects in the design process. At the same time, the NoC design ...
Deepwise Separable Convolution Support in Neural Network Platform

Mcmullen García, Brian Miguel (Universitat Politècnica de València, 2021-09-09)

[EN] In the last few years, Artificial intelligence (AI), has become an essential element of many technological fields. While AI has been developing on the level of algorithms, processing architectures have also been ...
Desarrollo de Algoritmos de Inteligencia Artificial y de Visión por Computador Optimizados para Sistemas FPGA

Catalán Gallach, Izan (Universitat Politècnica de València, 2020-09-28)

[ES] En este Trabajo Final de Máster se va a desarrollar el soporte para el uso de sistemas basados en FPGA en el proceso de tratamiento y filtrado de imágenes para aplicaciones médicas. En el TFM se utilizan las librerías ...
Desarrollo de Soporte de Procesos de Inferencia en FPGAs con High Level Synthesis

Ferrando Pla, Raúl (Universitat Politècnica de València, 2022-01-05)

[ES] En los últimos años la Inteligencia Artificial (AI) se ha convertido en un elemento imprescindible en múltiples ámbitos tecnológicos. Al mismo tiempo que la IA se está desarrollando a nivel de algoritmos, también las ...
Desarrollo de Soporte de Redes Recurrentes en Plataforma de Entrenamiento

Díaz Bou, Pere (Universitat Politècnica de València, 2021-09-28)

[ES] La investigación en inteligencia artificial está creciendo a un ritmo constante y gracias a ello, se están resolviendo problemas que hasta hace poco parecían imposibles. Las Redes Neuronales son unos de los algoritmos ...
Desarrollo de un Procesador de Altas Prestaciones para una Arquitectura Multinúcleo en FPGA #2

Picornell Sanjuan, Tomás (Universitat Politècnica de València, 2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...