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Browsing by Author "Flich Cardo, José"

Now showing items 1-20 of 56

A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs"

Bishnoi, Rimpy; Laxmi, Vijay; Gaur, Manoj Singh; Flich Cardo, José; Trivino, Francisco (Association for Computing Machinery (ACM), 2015-01)

[EN] In the Ghiribaldi et al. [2013] paper, a complete self-testing and self configuring NoC infrastructure for cost-effective MPSoCs was presented in order to make NoC architecture tolerant to faults. To overcome the ...
A communication-driven routing technique for application-specific NoCs

Tornero, Rafael; Orduña Huertas, Juan Manuel; Mejia, Andres; Flich Cardo, José; Duato Marín, José Francisco (Springer Verlag (Germany), 2011-06)

Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the ...
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs

Ghiribaldi, Alberto; Ludovici, Daniele; Triviño, Francisco; Strano, Alessandro; Flich Cardo, José; Sanchez Garcia, Jose Luis; Alfaro, Francisco; Favalli, Michelle; Bertozzi, Davide (Association for Computing Machinery (ACM), 2013-06)

[EN] Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and configuration strategy however implies two opposite requirements. One one hand, a fast and scalable ...
A low-latency modular switch for CMP systems

Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-11)

[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we ...
A survey and evaluation of topology-agnostic deterministic routing algorithms

Flich Cardo, José; Skeie, . Tor; Mejia, Andres; Lysne, . Olav; López Rodríguez, Pedro Juan; Robles Martínez, Antonio; Duato Marín, José Francisco; Koibuchi, . Michihiro; Rokicki, . Tomas; Sancho, . Jose Carlos (Institute of Electrical and Electronics Engineers (IEEE), 2012)

Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing algorithms, which make no assumption about the ...
An effective and feasible congestion management technique for high-performance MINs with tag-based distributed routing

Escudero-Sahuquillo, Jesús; Garcia Garcia, Pedro-Javier; Quiles Flor, Francisco Jose; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2013-10)

As parallel computing systems increase in size, the interconnection network is becoming a critical subsystem. The current trend in network design is to use as few components as possible to interconnect the end nodes, thereby ...
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Built-in fast gather control network for efficient support of coherence protocols

Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José (Institution of Engineering and Technology (IET), 2013-03)

[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
Characterizing the impact of process variation on 45 nm NoC-based CMPs

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-05)

[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Cost Effective Routing Implementations for On-chip Networks

Rodrigo Mocholí, Samuel (2010-11-29)

Arquitecturas de múltiples núcleos como multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) actuales se basan en la eficacia de las redes dentro del chip (NoC) para la comunicación ...
Cost-effective queue schemes for reducing head-of-line blocking in fat-trees

Escudero, Jesús; García García, Pedro Javier; Quiles Flor, Francisco Jose; Flich Cardo, José; Duato Marín, José Francisco (Wiley-Blackwell, 2011)

The fat-tree is one of the most common topologies among the interconnection networks of the systems currently used for high-performance parallel computing. Among other advantages, fat-trees allow the use of simple but very ...
Cost-efficient on-chip routing implementations for CMP and MPSoC systems

Rodrigo Mocholí, Samuel; Flich Cardo, José; Roca Pérez, Antoni; Medardoni, Simone; Bertozzi, Davide; Camacho Villanueva, Jesús; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-04)

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...
Desarrollo de un Procesador de Altas Prestaciones para una Arquitectura Multinúcleo en FPGA #2

Picornell Sanjuan, Tomás (2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...
Desarrollo de un procesador de altas prestaciones para una arquitectura multinúcleo en FPGAs #1

Guaita Masiá, Francisco (2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...
Desarrollo de un Procesador de Altas Prestaciones para una Arquitectura Multinúcleo en FPGAs #3

Lozano Torres, Raúl (2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...
Design and verification of a Systolic Array Multiplier

Andreu Cerezo, Pablo (2020-07-30)

[EN] Artificial intelligence aims to solve much of the problems of the contemporary society that we live in. But, in order for it to be ever so prevalent, the development of efficient inference-specific chips is needed, ...
Design, implementation, and analysis of router architectures and network topologies for FPGA-Based Multicore System

Juvaa, Boldbaatar (2015-09-29)

[EN] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads ...
Development of a Highly Capable Processor for a Multicore Architecture on FPGAs #4

Holland, Mark Antony (2015-07-31)

[EN] This project involves the design and implementation of a processor with outof-order execution using the Tomasulo algorithm. The processor is configurable, allowing a variable number of resources and functional units. ...
Diseño e implementación de las instrucciones multimedia en un procesador para un sistema multicore en FPGA

Cariñana Abasolo, Mario David (2015-03-23)

[ES] El presente trabajo tiene como objetivo simular el comportamiento de un procesador MIPS vectorial en una FPGA (Field Programmable Gate Array) multinúcleo. Para ello se implementa un juego de instrucciones multimedia ...
Diseño e implementación de soporte de calidad de servicio en arquitecturas multinúcleo

Picornell Sanjuan, Tomás (2016-07-25)

[EN] Networks on chip play a vital rol in application domains when QoS must be assured. Multicore systems, when running applications, need to guarantee certain levels of bandwidths and latency bounds for packet transmissions. ...