- -

Browsing by Author "Gil Tomás, Daniel Antonio"

RiuNet: Institutional repository of the Polithecnic University of Valencia

Browsing by Author "Gil Tomás, Daniel Antonio"

Sort by: Order: Results:

  • Icon
    Analyzing the impact of intermittent faults on microprocessors applying fault injection 
    Gil Tomás, Daniel Antonio; Gracia-Morán, Joaquín; Baraza Calvo, Juan Carlos; Saiz-Adalid, Luis-J.; Gil, Pedro (Institute of Electrical and Electronics Engineers (IEEE), 2012-12)
    Intermittent faults, being serious concerns for deep-submicron integrated circuits, are not well studied in the literature. This paper performs fault injection simulation to analyze the impact of intermittent faults, which ...
  • thumb
    Contribución a la validación de sistemas complejos tolerantes a fallos en la fase de diseño. Nuevos modelos de fallos y técnicas de inyección de fallos 
    Baraza Calvo, Juan Carlos (Universitat Politècnica de València, 2008-06-23)
    En el diseño de sistemas informáticos (y en particular, de aquéllos en los que, por las características del servicio que prestan, un mal funcionamiento puede provocar pérdida de vidas humanas, perjuicio económico, suspensión ...
  • thumb
    Design, Implementation and Evaluation of a Low Redundant Error Correction Code 
    Gracia-Morán, Joaquín; Saiz-Adalid, Luis-J.; Baraza-Calvo, Juan-Carlos; Gil Tomás, Daniel Antonio; Gil, Pedro (Institute of Electrical and Electronics Engineers, 2021-11)
    [EN] The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common ...
  • thumb
    Effects of intermittent faults on the reliability of a Reduced Instruction Set Computing (RISC) microprocessor 
    Gracia-Morán, Joaquín; Baraza Calvo, Juan Carlos; Gil Tomás, Daniel Antonio; Saiz-Adalid, Luis-J.; Gil, Pedro (Institute of Electrical and Electronics Engineers (IEEE), 2014-01-24)
    With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining ...
  • thumb
    Enhancement of fault injection techniques based on the modification of VHDL code 
    Baraza Calvo, Juan Carlos; Gracia-Morán, Joaquín; Blanc Clavero, Sara; Gil Tomás, Daniel Antonio; Gil Vicente, Pedro Joaquín (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior ...
  • thumb
    Estudio de nuevas tecnologías para memorias no volátiles emergentes 
    Aspas Coronado, Iván (Universitat Politècnica de València, 2019-10-17)
    [ES] Las tecnologías de memoria que constituyen el mercado actual están llegando a su límite de escalabilidad, y pronto la ley de Moore ya no podría aplicarse a estas tecnologías en su estado actual. La creciente demanda ...
  • thumb
    Fault Modeling of Graphene Nanoribbon FET Logic Circuits 
    Gil Tomás, Daniel Antonio; Gracia-Morán, Joaquín; Saiz-Adalid, Luis-J.; Gil, Pedro (MDPI AG, 2019-07-31)
    [EN] Due to the increasing defect rates in highly scaled complementary metal-oxide-semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. ...
  • thumb
    Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications 
    Gracia-Morán, Joaquín; Saiz-Adalid, Luis-J.; Gil Tomás, Daniel Antonio; Gil, Pedro (Institute of Electrical and Electronics Engineers, 2018)
    [EN] Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) ...
  • thumb
    Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System 
    Gil Tomás, Daniel Antonio; Gracia Morán, Joaquín; Baraza Calvo, Juan Carlos; Saiz Adalid, Luis José; Gil Vicente, Pedro Joaquín (Institute of Electrical and Electronics Engineers (IEEE), 2016-06)
    As scaling is more and more aggressive, intermittent faults are increasing their importance in current deep submicron complementary metal-oxide-semiconductor (CMOS) technologies. This work shows the dependability assessment ...
  • thumb
    Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM 
    Baraza Calvo, Juan Carlos; Gracia-Morán, Joaquín; Saiz-Adalid, Luis-J.; Gil Tomás, Daniel Antonio; Gil, Pedro (MDPI AG, 2020-12)
    [EN] Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its ...
  • thumb
    Reducing the Overhead of BCH Codes: New Double Error Correction Codes 
    Saiz-Adalid, Luis-J.; Gracia-Morán, Joaquín; Gil Tomás, Daniel Antonio; Baraza Calvo, Juan Carlos; Gil, Pedro (MDPI AG, 2020-11)
    [EN] The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word ...
  • thumb
    Studying the effects of intermittent faults on a microcontroller 
    Gil Tomás, Daniel Antonio; Gracia-Morán, Joaquín; Baraza Calvo, Juan Carlos; Saiz-Adalid, Luis-J.; Gil Vicente, Pedro Joaquín (Elsevier, 2012-11)
    As CMOS technology scales to the nanometer range, designers have to deal with a growing number and variety of fault types. Particularly, intermittent faults are expected to be an important issue in modern VLSI circuits. ...
  • thumb
    Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection 
    Saiz-Adalid, Luis-J.; Gracia-Morán, Joaquín; Gil Tomás, Daniel Antonio; Baraza Calvo, Juan Carlos; Gil, Pedro (Institute of Electrical and Electronics Engineers, 2019-10-14)
    [EN] Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs ...
  • thumb
    Validación por inyección de fallos en VHDL de la arquitectura TTA 
    Gracia Morán, Joaquín (Universitat Politècnica de València, 2010-04-20)
    La inyección de fallos es una técnica utilizada para la validación experimental de Sistemas Tolerantes a Fallos. Se distinguen tres grandes categorías: inyección de fallos física (denominada también physical fault injection ...