Espinosa García, Jaime; Hernández Luz, Carles; Abella, Jaume; Andrés Martínez, David de; Ruiz García, Juan Carlos(ACM, 2015-06)
Increasingly complex microcontroller designs for safety-relevant
automotive systems require the adoption of new methods
and tools to enable a cost-effective verification of their
robustness. In particular, costs associated ...
Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco(Elsevier, 2011-05)
[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Catalán Gallach, Izan(Universitat Politècnica de València, 2020-09-28)
[ES] En este Trabajo Final de Máster se va a desarrollar el soporte para el uso de sistemas
basados en FPGA en el proceso de tratamiento y filtrado de imágenes para aplicaciones
médicas.
En el TFM se utilizan las librerías ...
Andreu Cerezo, Pablo(Universitat Politècnica de València, 2020-07-30)
[EN] Artificial intelligence aims to solve much of the problems of the contemporary society that we live in. But, in order for it to be ever so prevalent, the development of efficient inference-specific chips is needed, ...
Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2011-12)
[EN] Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors
(CMPs). As the number of integrated cores in the chip increases the access to external memory becomes ...
Hernández Luz, Carles; Roca Pérez, Antoni; Silla Jiménez, Federico; Flich Cardo, José; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2012-02)
[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...
Cazorla, Francisco J.; Kosmidis, L.; Mezzetti, E.; Hernández Luz, Carles; Abella, Jaume; Vardanega, Tullio(Association for Computing Machinery, 2019-02)
[EN] The unabated increase in the complexity of the hardware and software components of modern embedded real-time systems has given momentum to a host of research in the use of probabilistic and statistical techniques for ...
[EN] Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most
vulnerable points for correct network operation and must be safeguarded against intra-link delay variations
and ...
Roca Pérez, Antoni; Hernández Luz, Carles; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco(Elsevier, 2013-08)
[EN] It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity ...
Espinosa García, Jaime; Andrés Martínez, David de; Ruiz García, Juan Carlos; Hernández Luz, Carles; Abella, Jaume(IEEE Conference Publications, 2015-09)
Safety-critical applications are required today to meet
more and more stringent standards than ever. In the need of
reducing the costs associated with the certification step, early
robustness evaluation can provide ...