RiuNet UPV Home
:
Browsing by Author

Search RiuNet

Browse

All of RiuNet

My Account

RiuNet Help

Admin. UPV

Browsing by Author "Hernández Luz, Carles"

Now showing items 1-20 of 28

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, Carles (Universitat Politècnica de València, 2012-07-19)
Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification

Espinosa García, Jaime; Hernández Luz, Carles; Abella, Jaume; Andrés Martínez, David de; Ruiz García, Juan Carlos (ACM, 2015-06)

Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated ...
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Characterizing the impact of process variation on 45 nm NoC-based CMPs

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-05)

[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Conflict-Free Networks on Chip for Real Time Systems

Picornell Sanjuan, Tomás (Universitat Politècnica de València, 2021-11-22)

[ES] La constante necesidad de un mayor rendimiento para cumplir con la gran demanda de potencia de cómputo de las nuevas aplicaciones, (ej. sistemas de conducción autónoma), obliga a la industria a apostar por la tecnología ...
Deepwise Separable Convolution Support in Neural Network Platform

Mcmullen García, Brian Miguel (Universitat Politècnica de València, 2021-09-09)

[EN] In the last few years, Artificial intelligence (AI), has become an essential element of many technological fields. While AI has been developing on the level of algorithms, processing architectures have also been ...
Desarrollo de Algoritmos de Inteligencia Artificial y de Visión por Computador Optimizados para Sistemas FPGA

Catalán Gallach, Izan (Universitat Politècnica de València, 2020-09-28)

[ES] En este Trabajo Final de Máster se va a desarrollar el soporte para el uso de sistemas basados en FPGA en el proceso de tratamiento y filtrado de imágenes para aplicaciones médicas. En el TFM se utilizan las librerías ...
Design and verification of a Systolic Array Multiplier

Andreu Cerezo, Pablo (Universitat Politècnica de València, 2020-07-30)

[EN] Artificial intelligence aims to solve much of the problems of the contemporary society that we live in. But, in order for it to be ever so prevalent, the development of efficient inference-specific chips is needed, ...
Development and design of a robotic data collection platform

Casas Lorenzo, Javier (Universitat Politècnica de València, 2023-09-25)

[ES] El objetivo de este proyecto de fin de grado (TFG) es el desarrollo y diseño de una plataforma robótica de recogida de datos. El proyecto se basará en el vehículo terrestre no tripulado (UGV) Clearpath Husky A200. ...
Development and design of a robotic perception system: Drivers, LiDAR-Camera Extrinsic Calibration, Data fusion and Dataset.

Gascón Bononad, Carlos (Universitat Politècnica de València, 2023-11-15)

[EN] The goal of this bachelor thesis (TFG) is the development and design of a robotic data collection platform. The project will be built upon the Clearpath Husky A200 Unmanned Ground Vehicle (UGV). This robot will be ...
Enforcing Predictability of Many-cores with DCFNoC

Picornell-Sanjuan, Tomás; Flich Cardo, José; Hernández Luz, Carles; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers, 2021-02-01)

[EN] The ever need for higher performance forces industry to include technology based on multi-processors system on chip (MPSoCs) in their safety-critical embedded systems. MPSoCs include a network-on-chip (NoC) to ...
Fault-tolerant vertical link design for effective 3D stacking

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-12)

[EN] Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes ...
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience

Flich Cardo, José; Tornero-Gavilá, Rafael; Rodríguez, D.; Russo, D.; Martínez Martínez, José María; Hernández Luz, Carles (IEEE, 2021-02-05)

[EN] In this paper we describe the evolution of the FPGA-based prototype deployed in the MANGO project, from a hardware prototyping platform of HPC architectures to a computing platform targeting HPC and AI applications. ...
Generación de un Módulo Optimizado de Inferencia en FPGAs con HLS

Medina Chaveli, Laura (Universitat Politècnica de València, 2021-12-13)

[ES] Las FPGAs (field-programmable gate array) pueden ser utilizadas para la inferencia de modelos de Redes Neuronales en sistemas embebidos, dado que este tipo de dispositivo presenta una alta eficiencia energética y un ...
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

Picornell-Sanjuan, Tomás; Flich Cardo, José; Duato Marín, José Francisco; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers, 2020)

[EN] The need for increasing the performance of critical real-time embedded systems pushes the industry to adopt complex multi-core processor designs with embedded networks-on-chip. In this paper we present hp-DCFNoC, a ...
Improving the Robustness of Redundant Execution with Register File Randomization

Tuzov, Ilya; Andreu, Pablo; Medina, Laura; Picornell-Sanjuan, Tomás; Robles Martínez, Antonio; López Rodríguez, Pedro Juan; Flich Cardo, José; Hernández Luz, Carles (IEEE, 2021-11-04)

[EN] Staggered Redundant execution (SRE) is a fault-tolerance mechanism that has been widely deployed in the context of safety-critical applications. SRE not only protects the system in the presence of faults but also helps ...
Locality-aware cache random replacement policies

Benedicte, Pedro; Hernández Luz, Carles; Abella, Jaume; Cazorla, Francisco J. (Elsevier, 2019-02)

[EN] Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs ...
Measuring and Controlling Multicore Contention in a RISC-V System-on-Chip

Andreu Cerezo, Pablo (Universitat Politècnica de València, 2021-09-30)

[ES] Los procesadores multinúcleo empezaron una revolución en el cómputo moderno cuando fueron introducidos en el espacio de cómputo comercial y de consumidor. Estos procesadores multinúcleo presentaban un aumento significativo ...
On the impact of within-die process variation in GALS-Based NoC Performance

Hernández Luz, Carles; Roca Pérez, Antoni; Silla Jiménez, Federico; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-02)

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...
Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives

Canal, Ramon; Hernández Luz, Carles; Tornero-Gavilá, Rafael; Cilardo, Alessandro; Massari, Giuseppe; Reghenzani, Federico; Fornaciari, William; Zapater, Marina; Atienza, David; Oleksiak, Ariel; Piatek, Wojciech; Abella, Jaume (Association for Computing Machinery, 2020-10)

[EN] Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, ...