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Browsing by Author "Hernández Luz, Carles"

Now showing items 1-20 of 21

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, Carles (Universitat Politècnica de València, 2012-07-19)
Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification

Espinosa García, Jaime; Hernández Luz, Carles; Abella, Jaume; Andrés Martínez, David de; Ruiz García, Juan Carlos (ACM, 2015-06)

Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated ...
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Characterizing the impact of process variation on 45 nm NoC-based CMPs

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-05)

[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Deepwise Separable Convolution Support in Neural Network Platform

Mcmullen García, Brian Miguel (Universitat Politècnica de València, 2021-09-09)

[EN] In the last few years, Artificial intelligence (AI), has become an essential element of many technological fields. While AI has been developing on the level of algorithms, processing architectures have also been ...
Desarrollo de Algoritmos de Inteligencia Artificial y de Visión por Computador Optimizados para Sistemas FPGA

Catalán Gallach, Izan (Universitat Politècnica de València, 2020-09-28)

[ES] En este Trabajo Final de Máster se va a desarrollar el soporte para el uso de sistemas basados en FPGA en el proceso de tratamiento y filtrado de imágenes para aplicaciones médicas. En el TFM se utilizan las librerías ...
Design and verification of a Systolic Array Multiplier

Andreu Cerezo, Pablo (Universitat Politècnica de València, 2020-07-30)

[EN] Artificial intelligence aims to solve much of the problems of the contemporary society that we live in. But, in order for it to be ever so prevalent, the development of efficient inference-specific chips is needed, ...
Enforcing Predictability of Many-cores with DCFNoC

Picornell-Sanjuan, Tomás; Flich Cardo, José; Hernández Luz, Carles; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers, 2021-02-01)

[EN] The ever need for higher performance forces industry to include technology based on multi-processors system on chip (MPSoCs) in their safety-critical embedded systems. MPSoCs include a network-on-chip (NoC) to ...
Fault-tolerant vertical link design for effective 3D stacking

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-12)

[EN] Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes ...
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

Picornell-Sanjuan, Tomás; Flich Cardo, José; Duato Marín, José Francisco; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers, 2020)

[EN] The need for increasing the performance of critical real-time embedded systems pushes the industry to adopt complex multi-core processor designs with embedded networks-on-chip. In this paper we present hp-DCFNoC, a ...
Locality-aware cache random replacement policies

Benedicte, Pedro; Hernández Luz, Carles; Abella, Jaume; Cazorla, Francisco J. (Elsevier, 2019-02)

[EN] Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs ...
Measuring and Controlling Multicore Contention in a RISC-V System-on-Chip

Andreu Cerezo, Pablo (Universitat Politècnica de València, 2021-09-30)

[ES] Los procesadores multinúcleo empezaron una revolución en el cómputo moderno cuando fueron introducidos en el espacio de cómputo comercial y de consumidor. Estos procesadores multinúcleo presentaban un aumento significativo ...
On the impact of within-die process variation in GALS-Based NoC Performance

Hernández Luz, Carles; Roca Pérez, Antoni; Silla Jiménez, Federico; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-02)

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...
Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives

Canal, Ramon; Hernández Luz, Carles; Tornero-Gavilá, Rafael; Cilardo, Alessandro; Massari, Giuseppe; Reghenzani, Federico; Fornaciari, William; Zapater, Marina; Atienza, David; Oleksiak, Ariel; Piatek, Wojciech; Abella, Jaume (Association for Computing Machinery, 2020-10)

[EN] Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, ...
Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey

Cazorla, Francisco J.; Kosmidis, L.; Mezzetti, E.; Hernández Luz, Carles; Abella, Jaume; Vardanega, Tullio (Association for Computing Machinery, 2019-02)

[EN] The unabated increase in the complexity of the hardware and software components of modern embedded real-time systems has given momentum to a host of research in the use of probabilistic and statistical techniques for ...
SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems.

Hernández Luz, Carles; Flich Cardo, José; Paredes Palacios, Roberto; Lefebvre, Charles-Alexis; Allende, Imanol; Abella, Jaume; Trilla, David; Matschnig, Martin; Fischer, Bernhard; Schwarz, Konrad; Kiszka, Jan; Ronnback, Martin; Klockars, Johan; McGuire, Nicholas; Rammerstorfer, Franz (IEEE, 2020-08-28)

[Otros] xisting HW/SW platforms for safety-critical systems suffer from limited performance and/or from lack of flexibility due to building on specific proprietary components. This jeopardizes their wide deployment across ...
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Strano, Alessandro; Hernández Luz, Carles; Silla Jiménez, Federico; Bertozzzi, Davide (IGI Global, 2011)

[EN] Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and ...
Silicon-aware distributed switch architecture for on-chip networks

Roca Pérez, Antoni; Hernández Luz, Carles; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2013-08)

[EN] It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity ...
Suport Eficient de Processos d’Inferència en Plataforme Heterogènies

Iznardo Ruiz, Alejandro (Universitat Politècnica de València, 2021-09-20)

[CA] La intel·ligència artificial i les seues variants estan evolucionant ràpidament i millorant molts aspectes de la vida humana, tant en aplicacions industrials com en usos quotidians. Per aquest motiu, molts investigadors ...
The RECIPE approach to challenges in deeply heterogeneous high performance systems

Agosta, Giovanni; Fornaciari, William; Atienza, David; Canal, Ramon; Cilardo, Alessandro; Flich Cardo, José; Hernández Luz, Carles; Kulczewski, Michal; Massari, Giuseppe; Tornero-Gavilá, Rafael; Zapater, Marina (Elsevier, 2020-09)

[EN] RECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring ...