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Browsing by Subject "Computer architecture"

Now showing items 1-16 of 16

5G Radio Access Networks Enabling Efficient Point-to-Multipoint Transmissions

Säily, Mikko; Barjau, Carlos; Navrátil, David; Prasad, Athul; Gomez-Barquero, David; Tesema, Fasil B. (Institute of Electrical and Electronics Engineers, 2019-12)

[EN] The first release of 5th Generation (5G) technology from 3rd Generation Project Partnership (3GPP) Rel'15 has been completed in December 2018. An open issue with this release of standards is that it only supports ...
A UAV-Based Content Delivery Architecture for Rural Areas and Future Smart Cities

Ortiz-Mayordomo, Sergio; Tavares De Araujo Cesariny Calafate, Carlos Miguel; Cano, Juan-Carlos; Manzoni, Pietro; Toh, C.K. (Institute of Electrical and Electronics Engineers, 2019-03-06)

[EN] Content delivery in vehicular environments can serve multiple purposes, such as safety, entertainment, and news delivery that can be geographically relevant to vehicles traveling within a certain area. The traditional ...
Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, Carles (Universitat Politècnica de València, 2012-07-19)
Bringing Real Processorsto Labs

Gómez Requena, Crispín; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Wiley, 2015-09)

The architecture of current processors has experienced great changes in the last years, leading to sophisticated multithreaded multicore processors. The inherent complexity of such processors makes difficult to update ...
Control inteligente mediante escalado dinámico voltaje-frecuencia (DVFS) de la temperatura en procesadores embebidos

Hernández-Almudi, P.; Suárez, D.; Montijano, E.; Merino, J. (Universitat Politècnica de València, 2021-09-30)

[EN] The increment in computing power of embedded processors has fueled a revolution in many application domains such as mobile computing or robotics. Dissipating the energy consumed by those processors on a very small ...
Design and implementation of a parameterized Out-of-Order RISC-V processor with a new toolflow

Tamarit Camarero, Cecilio César (Universitat Politècnica de València, 2020-09-28)

[ES] Dada la actual necesidad de innovación a nivel arquitectural, es necesario contar con herramientas y metodologías eficientes para validar y evaluar nuevos diseños. En el ámbito de este TFM se ha diseñado e implementado ...
Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective

Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente (Elsevier, 2018)

[EN] Computer architecture courses typically include lab sessions to reinforce, from a practical perspective, concepts and architectural mechanisms studied in lectures. Lab sessions are mainly based on simulation frameworks ...
Diseño e implementación de entorno de ejecución para sistemas embebidos con arquitectura ARM Cortex-A

Llano Sánchez, Leandro Rafael (Universitat Politècnica de València, 2020-10-13)

[ES] Cada vez más los sistemas embebidos tienen mayor relevancia en la vida cotidiana, están presente alrededor de todos y en las cosas que menos se piensan. Debido al gran uso de estos sistemas, en el mundo laboral ...
Influence of InfiniBand FDR on the performance of remote GPU virtualization

Reaño González, Carlos; Mayo Gual, Rafael; Quintana Ortí, Enrique Salvador; Silla Jiménez, Federico; Duato Marín, José Francisco; Peña Monferrer, Antonio José (IEEE, 2013-09-23)

The use of GPUs to accelerate general-purpose scientific and engineering applications is mainstream today, but their adoption in current high-performance computing clusters is impaired primarily by acquisition costs and ...
Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors

Puche Lara, José (Universitat Politècnica de València, 2021-04-13)

[ES] Los procesadores multinúcleo actuales cuentan con recursos compartidos entre los diferentes núcleos. Dos de estos recursos compartidos, la cache de último nivel y el ancho de banda de memoria principal, pueden convertirse ...
Optimización de arquitecturas distribuidas para el procesado de datos masivos

Herrera Hernández, José (Universitat Politècnica de València, 2020-09-02)

[ES] La utilización de sistemas para el tratamiento eficiente de grandes volúmenes de información ha crecido en popularidad durante los últimos años. Esto conlleva el desarrollo de nuevas tecnologías, métodos y algoritmos, ...
Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

Lodde, Mario (Universitat Politècnica de València, 2014-02-04)

La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo ...
Speaker-Adapted Confidence Measures for ASR using Deep Bidirectional Recurrent Neural Networks

Del Agua Teba, Miguel Angel; Giménez Pastor, Adrián; Sanchis Navarro, José Alberto; Civera Saiz, Jorge; Juan, Alfons (Institute of Electrical and Electronics Engineers, 2018)

[EN] In the last years, Deep Bidirectional Recurrent Neural Networks (DBRNN) and DBRNN with Long Short-Term Memory cells (DBLSTM) have outperformed the most accurate classifiers for confidence estimation in automatic speech ...
TACASHI: Trust-Aware Communication Architecture for Social Internet of Vehicles

Kerrache, Chaker Abdelaziz; Lagraa, Nasreddine; Hussain, Rasheed; Ahmed, Syed Hassan; Benslimane, Abderrahim; Tavares De Araujo Cesariny Calafate, Carlos Miguel; Cano, Juan-Carlos; Vegni, Anna Maria (Institute of Electrical and Electronics Engineers, 2019-08)

[EN] The Internet of Vehicles (IoV) has emerged as a new spin-off research theme from traditional vehicular ad hoc networks. It employs vehicular nodes connected to other smart objects equipped with a powerful multisensor ...
Tridimensional block multiword LDPC decoding on GPUs

Martínez Zaldívar, Francisco José; Vidal Maciá, Antonio Manuel; González Salvador, Alberto; Almenar Terré, Vicenç (Springer Verlag (Germany), 2011-12)

[EN] In this paper, we describe a parallel algorithm for LDPC (Low Density Parity Check codes) decoding on a GPU (Graphics Processing Unit) using CUDA (Compute Unified Device Architecture). The strategy of the kernel grid ...
VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors

Feliu-Pérez, Josué; Naithani, Ajeya; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Qureshi, Moinuddin; Eeckhout, Lieven (Institute of Electrical and Electronics Engineers, 2022-06-01)

[EN] Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively ...