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Browsing by Subject "Memory hierarchy"

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Browsing by Subject "Memory hierarchy"

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    Adaptive prefetch for multicores 
    Selfa Oliver, Vicent (Universitat Politècnica de València, 2016-01-08)
    [EN] Current multicore systems implement various hardware prefetchers since prefetching can significantly hide the huge main memory latencies. However, memory bandwidth is a scarce resource which becomes critical with ...
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    Critical Phase-Aware Partitioning Approach (CPA) 
    Pons Escat, Lucía; Selfa Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Pons Terol, Julio (Universitat Politècnica de València, 2020-05-14)
    CPA is LLC (Last Level Cache) partitioning approach that performs an efficient cache space distribution among executing applications. To assign partitions (ways) of the LLC, Intel CAT is used. This policy is included in a ...
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    Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance 
    Candel-Margaix, Francisco; Valero Bresó, Alejandro; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio (Institute of Electrical and Electronics Engineers, 2019-10-01)
    [EN] To support the massive amount of memory accesses that GPGPU applications generate, GPU memory hierarchies are becoming more and more complex, and the Last Level Cache (LLC) size considerably increases each GPU generation. ...
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    LUT saving in embedded FPGAs for cache locking in real-time systems 
    Martí Campoy, Antonio; Rodríguez Ballester, Francisco; Ors Carot, Rafael (2013)
    [EN] In recent years, cache locking have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular ...
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    Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors 
    Puche Lara, José (Universitat Politècnica de València, 2021-04-13)
    [ES] Los procesadores multinúcleo actuales cuentan con recursos compartidos entre los diferentes núcleos. Dos de estos recursos compartidos, la cache de último nivel y el ancho de banda de memoria principal, pueden convertirse ...
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    Planificación de tareas considerando la contención en la jerarquía de memoria de procesadores multinúcleo 
    Feliu Pérez, Josué (Universitat Politècnica de València, 2013-02-25)
    [ES] Con el objetivo de mejorar el rendimiento de los CMPs, parte de la investigación reciente se ha centrado en la planificación de procesos para limitar la contención provocada por el limitado ancho de banda. Hoy en dia, ...