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dc.contributor.author | Petit Martí, Salvador Vicente | es_ES |
dc.contributor.author | Sahuquillo Borrás, Julio | es_ES |
dc.contributor.author | Gómez Requena, María Engracia | es_ES |
dc.contributor.author | Selfa-Oliver, Vicent | es_ES |
dc.date.accessioned | 2018-05-14T04:18:17Z | |
dc.date.available | 2018-05-14T04:18:17Z | |
dc.date.issued | 2017 | es_ES |
dc.identifier.issn | 0743-7315 | es_ES |
dc.identifier.uri | http://hdl.handle.net/10251/101889 | |
dc.description.abstract | [EN] The fast evolution of multicore processors makes it difficult for professors to offer computer architecture courses with updated contents. To deal with this shortcoming that could discourage students, the most appropriate solution is a research-oriented course based on current microprocessor industry trends. Additionally, we also seek to improve the students' skills by applying active learning methodologies, where teachers act as guiders and resource providers while students take the responsibility for their learning. In this paper, we present the Advanced Multicore Architecture (AMA) course, which follows a research-oriented approach to introduce students in architectural breakthroughs and uses active learning methodologies to enable students to develop practical research skills such as critical analysis of research papers or communication abilities. To this end five main activities are used: (i) lectures dealing with key theoretical concepts, (ii) paper review & discussion, (iii) research-oriented practical exercises, (iv) lab sessions with a state-of-the-art multicore simulator, and (v) paper presentation. An important part of all these activities is driven by active learning methodologies. Special emphasis is put on the practical side by allocating 40% of the time to labs and exercises. This work also includes an assessment study that analyzes both the course contents and the used methodology (both of them compared to other courses). | es_ES |
dc.description.sponsorship | This work was supported in part by the Spanish Ministerio de Economia y Competitividad (MINECO) and by Plan E funds under Grant TIN2014-62246-EXP and Grant TIN2015-66972-C5-1-R, and by Generalitat Valenciana under grant AICO/2016/059. Authors also would like to thank Onur Mutlu for making available online his valuable teaching material. | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Elsevier | es_ES |
dc.relation.ispartof | Journal of Parallel and Distributed Computing | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Advanced computer architecture courses | es_ES |
dc.subject | Teaching methods | es_ES |
dc.subject | Research-oriented method | es_ES |
dc.subject | Lab sessions | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1016/j.jpdc.2017.01.011 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2014-62246-EXP/ES/CODISEÑO HARDWARE-SOFTWARE PARA PLANIFICACION EQUITATIVA EN PROCESADORES SMT MULTINUCLEO/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2015-66972-C5-1-R/ES/TECNICAS PARA LA MEJORA DE LAS PRESTACIONES, COSTE Y CONSUMO DE ENERGIA DE LOS SERVIDORES/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/GVA//AICO%2F2016%2F059/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.date.embargoEndDate | 2019-07-01 | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Petit Martí, SV.; Sahuquillo Borrás, J.; Gómez Requena, ME.; Selfa-Oliver, V. (2017). A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies. Journal of Parallel and Distributed Computing. 105:63-72. https://doi.org/10.1016/j.jpdc.2017.01.011 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | https://doi.org/10.1016/j.jpdc.2017.01.011 | es_ES |
dc.description.upvformatpinicio | 63 | es_ES |
dc.description.upvformatpfin | 72 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 105 | es_ES |
dc.relation.pasarela | S\359592 | es_ES |
dc.contributor.funder | Generalitat Valenciana | es_ES |
dc.contributor.funder | Ministerio de Economía, Industria y Competitividad | es_ES |