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The Tag Filter Architecture: An energy-efficient cache and directory design

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The Tag Filter Architecture: An energy-efficient cache and directory design

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dc.contributor.author Valls, Joan es_ES
dc.contributor.author Ros Bardisa, Alberto es_ES
dc.contributor.author Gómez Requena, María Engracia es_ES
dc.contributor.author Sahuquillo Borrás, Julio es_ES
dc.date.accessioned 2018-05-14T04:22:33Z
dc.date.available 2018-05-14T04:22:33Z
dc.date.issued 2017 es_ES
dc.identifier.issn 0743-7315 es_ES
dc.identifier.uri http://hdl.handle.net/10251/101903
dc.description.abstract [EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major design concern that aggravates with the current trend of increasing the core count. A significant fraction of the total power budget is consumed by on-chip caches which are usually deployed with a high associativity degree (even L1 caches are being implemented with eight ways) to enhance the system performance. On a cache access, each way in the corresponding set is accessed in parallel, which is costly in terms of energy. On the other hand, coherence protocols also must implement efficient directory caches that scale in terms of power consumption. Most of the state-of-the-art techniques that reduce the energy consumption of directories are at the cost of performance, which may become unacceptable for high-performance CMPs. In this paper, we propose an energy-efficient architectural design that can be effectively applied to any kind of cache memory. The proposed approach, called the Tag Filter (TF) Architecture, filters the ways accessed in the target cache set, and just a few ways are searched in the tag and data arrays. This allows the approach to reduce the dynamic energy consumption of caches without hurting their access time. For this purpose, the proposed architecture holds the XX least significant bits of each tag in a small auxiliary X-bit-wide array. These bits are used to filter the ways where the least significant bits of the tag do not match with the bits in the X-bit array. Experimental results show that, on average, the TF Architecture reduces the dynamic power consumption across the studied applications up to 74.9%74.9%, 85.9%85.9%, and 84.5%84.5% when applied to L1 caches, L2 caches, and directory caches, respectively. es_ES
dc.description.sponsorship This work has been jointly supported by MINECO and European Commission (FEDER funds) under the project TIN2015-66972-C5-1-R/3-R and by Fundación Séneca, Agencia de Ciencia y Tecnología de la Región de Murcia under the project Jóvenes Líderes en Investigación 18956/JLI/13.
dc.language Inglés es_ES
dc.publisher Elsevier es_ES
dc.relation MINECO/TIN2015-66972-C5-1-R es_ES
dc.relation.ispartof Journal of Parallel and Distributed Computing es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Multicore processors es_ES
dc.subject Cache es_ES
dc.subject Directory es_ES
dc.subject Dynamic consumption es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title The Tag Filter Architecture: An energy-efficient cache and directory design es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1016/j.jpdc.2016.04.016 es_ES
dc.rights.accessRights Abierto es_ES
dc.date.embargoEndDate 2019-02-01 es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Valls, J.; Ros Bardisa, A.; Gómez Requena, ME.; Sahuquillo Borrás, J. (2017). The Tag Filter Architecture: An energy-efficient cache and directory design. Journal of Parallel and Distributed Computing. 100:193-202. doi:10.1016/j.jpdc.2016.04.016 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion https://doi.org/10.1016/j.jpdc.2016.04.016 es_ES
dc.description.upvformatpinicio 193 es_ES
dc.description.upvformatpfin 202 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 100 es_ES
dc.relation.pasarela S\312850 es_ES
dc.contributor.funder Ministerio de Economía, Industria y Competitividad es_ES


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