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Precise Runahead Execution

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Naithani, A.; Feliu-Pérez, J.; Adileh, A.; Eeckhout, L. (2019). Precise Runahead Execution. IEEE Computer Architecture Letters. 18(1):71-74. https://doi.org/10.1109/LCA.2019.2910518

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/157199

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Title: Precise Runahead Execution
Author: Naithani, Ajeya Feliu-Pérez, Josué Adileh, Almutaz Eeckhout, Lieven
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
[EN] Runahead execution improves processor performance by accurately prefetching long-latency memory accesses. When a long-latency load causes the instruction window to fill up and halt the pipeline, the processor enters ...[+]
Subjects: Microarchitecture , Single-core performance , Runahead execution
Copyrigths: Reserva de todos los derechos
IEEE Computer Architecture Letters. (issn: 1556-6056 )
DOI: 10.1109/LCA.2019.2910518
Institute of Electrical and Electronics Engineers
Publisher version: https://doi.org/10.1109/LCA.2019.2910518
Project ID:
info:eu-repo/grantAgreement/EC/H2020/741097/EU/Load Slice Core: A Power and Cost-Efficient Microarchitecture for the Future/
Description: © 2019 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
This research is supported through FWO grants no. G.0434.16N and G.0144.17N, and European Research Council (ERC) Advanced Grant agreement no. 741097.
Type: Artículo



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