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Built-in fast gather control network for efficient support of coherence protocols

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Built-in fast gather control network for efficient support of coherence protocols

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Lodde, M.; Roca Pérez, A.; Flich Cardo, J. (2013). Built-in fast gather control network for efficient support of coherence protocols. IET Computers and Digital Techniques. 7(2):69-80. doi:10.1049/iet-cdt.2012.0056

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/38668

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Title: Built-in fast gather control network for efficient support of coherence protocols
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Universitat Politècnica de València. Grupo de Arquitecturas Paralelas
Issued date:
Abstract:
[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...[+]
Subjects: Microprocessor chips , Network-on-chip , Protocols , Shared memory systems
Copyrigths: Cerrado
Source:
IET Computers and Digital Techniques. (issn: 1751-8601 )
DOI: 10.1049/iet-cdt.2012.0056
Publisher:
Institution of Engineering and Technology (IET)
Publisher version: http://dx.doi.org/10.1049/iet-cdt.2012.0056
Conference name: 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC) 2012
Conference place: Paris, France
Conference date: January 22, 2012
Project ID: info:eu-repo/grantAgreement/EC/FP7/288574 info:eu-repo/grantAgreement/EC/FP7/287759/EU
Thanks:
This work has been supported by the VIRTICAL project (grant agreement n 288574) which is funded by the European Commission within the Research Programme FP7.
Type: Artículo

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