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Built-in fast gather control network for efficient support of coherence protocols

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Built-in fast gather control network for efficient support of coherence protocols

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dc.contributor.author Lodde, Mario es_ES
dc.contributor.author Roca Pérez, Antoni es_ES
dc.contributor.author Flich Cardo, José es_ES
dc.date.accessioned 2014-07-08T11:33:11Z
dc.date.issued 2013-03
dc.identifier.issn 1751-8601
dc.identifier.uri http://hdl.handle.net/10251/38668
dc.description.abstract [EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re-organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast-based protocol (Hammer). Experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. Simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70 and 40%, respectively. es_ES
dc.description.sponsorship This work has been supported by the VIRTICAL project (grant agreement n 288574) which is funded by the European Commission within the Research Programme FP7.
dc.format.extent 12 es_ES
dc.language Inglés es_ES
dc.publisher Institution of Engineering and Technology (IET) es_ES
dc.relation.ispartof IET Computers and Digital Techniques es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Microprocessor chips es_ES
dc.subject Network-on-chip es_ES
dc.subject Protocols es_ES
dc.subject Shared memory systems es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Built-in fast gather control network for efficient support of coherence protocols es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1049/iet-cdt.2012.0056
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/288574 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/287759/EU
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.contributor.affiliation Universitat Politècnica de València. Grupo de Arquitecturas Paralelas es_ES
dc.description.bibliographicCitation Lodde, M.; Roca Pérez, A.; Flich Cardo, J. (2013). Built-in fast gather control network for efficient support of coherence protocols. IET Computers and Digital Techniques. 7(2):69-80. doi:10.1049/iet-cdt.2012.0056 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.conferencename 6th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC) 2012
dc.relation.conferencedate January 22, 2012
dc.relation.conferenceplace Paris, France
dc.relation.publisherversion http://dx.doi.org/10.1049/iet-cdt.2012.0056 es_ES
dc.description.upvformatpinicio 69 es_ES
dc.description.upvformatpfin 80 es_ES
dc.type.version info:eu repo/semantics/publishedVersion es_ES
dc.description.volume 7 es_ES
dc.description.issue 2 es_ES
dc.relation.senia 264525
dc.contributor.funder European Commission


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