García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J.; Flanagan, MF. (2012). Serial symbol-reliability based algorithm for decoding non-binary LDPC codes. IEEE Communications Letters. 16(6):909-912. https://doi.org/10.1109/LCOMM.2012.040912.120423
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/47023
Título:
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Serial symbol-reliability based algorithm for decoding non-binary LDPC codes
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Autor:
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García Herrero, Francisco Miguel
Canet Subiela, Mª José
Valls Coquillat, Javier
Flanagan, Mark F.
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Entidad UPV:
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Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
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Fecha difusión:
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Resumen:
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A symbol-reliability based decoding algorithm with serial schedule for non-binary low-density parity-check (LDPC) codes is presented. Performance results, together with implementation complexity analysis, are provided for ...[+]
A symbol-reliability based decoding algorithm with serial schedule for non-binary low-density parity-check (LDPC) codes is presented. Performance results, together with implementation complexity analysis, are provided for different sample codes. The proposed algorithm achieves a similar gain to the min-max algorithm for codes with column weight d(v) >= 6, with lower complexity than previous symbol-reliability based algorithms.
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Palabras clave:
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Iterative serial decoding
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Nonbinary low-density parity-check (LDPC) code
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Symbol-reliability based algorithm
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Decoding algorithm
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Implementation complexity
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Low-density parity-check (LDPC) codes
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Lower complexity
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Min-max
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Non-binary
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Non-binary LDPC codes
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Error correction
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Forward error correction
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Reliability
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Scheduling algorithms
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Iterative decoding
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Derechos de uso:
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Cerrado |
Fuente:
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IEEE Communications Letters. (issn:
1089-7798
)
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DOI:
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10.1109/LCOMM.2012.040912.120423
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Editorial:
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Institute of Electrical and Electronics Engineers (IEEE)
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Versión del editor:
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http://dx.doi.org/10.1109/LCOMM.2012.040912.120423
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Código del Proyecto:
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info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/
info:eu-repo/grantAgreement/GVA//ACIF%2F2011%2F023/
info:eu-repo/grantAgreement/MECD//AP2010-5178/ES/AP2010-5178/
info:eu-repo/grantAgreement/UPV//PAID-00-11/
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Agradecimientos:
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This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2011-27916. F. Garcia-Herrero has developed his work in this project thanks to a VALi+d grant sponsored by Generalitat ...[+]
This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2011-27916. F. Garcia-Herrero has developed his work in this project thanks to a VALi+d grant sponsored by Generalitat Valenciana (Conselleria d'Educacio) Grant No. ACIF/2011/023, and a FPU grant sponsored by the Spanish Government Grant No. AP2010-5178. M. J. Canet has developed her work in this project thanks to Programa de Apoyo a la Investigacion y Desarrollo (PAID-00-11) sponsored by Universidad Politcenica de Valencia and Programa Nacional de Movilidad de Recursos Humanos del Plan Nacional de I-D+i 2008-2011 supported by Ministerio de Educacion.
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Tipo:
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Artículo
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