Lacruz Jucht, Jesús OmarGarcía Herrero, Francisco MiguelCanet Subiela, Mª JoséValls Coquillat, JavierPérez Pascual, Mª Asunción2016-09-292016-09-292015-07978-147998391-90271-4310https://riunet.upv.es/handle/10251/70703A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.Reserva de todos los derechosNon-binary LDPCDecoderFPGATECNOLOGIA ELECTRONICAComunicación en congreso10.1109/ISCAS.2015.7169065Abierto