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Listar por autor "Roca Pérez, Antoni"

Mostrando ítems 1-10 de 10

A low-latency modular switch for CMP systems

Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-11)

[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we ...
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Built-in fast gather control network for efficient support of coherence protocols

Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José (Institution of Engineering and Technology (IET), 2013-03)

[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
Characterizing the impact of process variation on 45 nm NoC-based CMPs

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-05)

[EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
Cost-efficient on-chip routing implementations for CMP and MPSoC systems

Rodrigo Mocholí, Samuel; Flich Cardo, José; Roca Pérez, Antoni; Medardoni, Simone; Bertozzi, Davide; Camacho Villanueva, Jesús; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-04)

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...
Efficient routing in heterogeneous SoC designs with small implementation overhead

Cano Reyes, José; Flich Cardo, José; Roca Pérez, Antoni; Duato Marín, José Francisco; Coppola, Marcello; Locatelli, Riccardo (Institute of Electrical and Electronics Engineers (IEEE), 2014-03)

In application-specific SoCs, the irregularity of the topology ends up in a complex and customized implementation of the routing algorithm, usually relying on routing tables implemented with memory structures at source end ...
Fault-tolerant vertical link design for effective 3D stacking

Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-12)

[EN] Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes ...
Floorplan-Aware High Performance NoC Design

Roca Pérez, Antoni (Universitat Politècnica de València, 2012-11-20)

Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes dentro del chip (NoC) como elemento -ptimo ...
On the impact of within-die process variation in GALS-Based NoC Performance

Hernández Luz, Carles; Roca Pérez, Antoni; Silla Jiménez, Federico; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-02)

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...
Silicon-aware distributed switch architecture for on-chip networks

Roca Pérez, Antoni; Hernández Luz, Carles; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2013-08)

[EN] It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity ...