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Listar por autor "García Herrero, Francisco Miguel"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por autor "García Herrero, Francisco Miguel"

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    A 630 Mbps non-binary decoder for FPGA 
    Lacruz Jucht, Jesús Omar; García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier; Pérez Pascual, Mª Asunción (IEEE, 2015-07)
    A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of ...
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    A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding 
    Valls Coquillat, Javier; Torres Carot, Vicente; Canet Subiela, Mª José; García-Herrero, Francisco M. (Institute of Electrical and Electronics Engineers, 2019-06)
    [EN] This paper presents a low-complexity chase (LCC) decoder for Reed-Solomon (RS) codes, which uses a novel method for the selection of test vectors that is based on the analysis of the symbol error probabilities derived ...
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    Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes 
    García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Springer Verlag (Germany), 2013-04)
    A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modifed to avoid ...
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    Architectures for soft-decision decoding of non-binary codes 
    García Herrero, Francisco Miguel (Universitat Politècnica de València, 2013-11-19)
    En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los ...
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    Decodificador de códigos LDPC no binarios basado en el algoritmo T-EMS 
    Lacruz Jucht, Jesús Omar (Universitat Politècnica de València, 2014-11-24)
    [EN] In this work a non-binary LDPC decoder based on T-EMS algorithm is proposed. A full parallel architecture of the check node has been implemented and a layered schedule is used for the decoder. The proposed decoder has ...
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    Design and implementation of decoders for error correction in high-speed communication systems 
    Català Pérez, Joan Marc (Universitat Politècnica de València, 2017-09-01)
    This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in ...
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    Diseño e implementación en FPGA de un decodificador Reed-Solomon de alta velocidad 
    García Herrero, Francisco Miguel (Universitat Politècnica de València, 2015-12-17)
    La finalidad principal del proyecto es el diseño e implementación de un decodificador Reed-Solomon de alta velocidad, no obstante existen una serie de objetivos intermedios que es necesario cumplir, para alcazar esta ...
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    High speed RS(255, 239) decoder based on LCC decoding 
    García Herrero, Francisco Miguel; Valls Coquillat, Javier; Meher, P. K. (Springer Verlag (Germany), 2011-12)
    Algebraic Soft-Decision Decoding (ASD) of Reed-Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, ...
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    High-Performance NB-LDPC Decoder With Reduction of Message Exchange 
    Lacruz, Jesus O.; García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016-05)
    This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node ...
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    High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes 
    García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier; Meher, Pramod Kumar (Institute of Electrical and Electronics Engineers (IEEE), 2012-03)
    In this paper, a high-throughput interpolator architecture for soft-decision decoding of Reed-Solomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We have formulated a modified form of the Nielson's ...
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    Interpolador para decodificador Reed Solomon soft-decision de alta velocidad 
    García Herrero, Francisco Miguel (Universitat Politècnica de València, 2011-11-29)
    Se presentan dos arquitecturas para interpoladores de decodificación soft-decision basada en los códigos Reed-Solomon y que recurre al algoritmo Chase de Baja Complejidad (LCC). La primera es una arquitectura paralela ...
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    Multiple-vote symbol flipping decoder for non-binary LDPC codes 
    García Herrero, Francisco Miguel; Li, Erbao; Declercq, David; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2014-11)
    A multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering ...
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    Non-binary LDPC decoder based on simplified enhanced generalized bit flipping algorithm 
    García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2014-06)
    A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB ...
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    Non-binary LDPC decoder based on symbol flipping with multiple votes 
    García Herrero, Francisco Miguel; Declercq, D.; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2014-05)
    In this letter, a new algorithm to decode non-binary LDPC (NB-LDPC) codes is proposed. This algorithm is inspired from very low complexity decoders that have been proposed recently, in which only syndrome computations at ...
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    One minimum only trellis decoder for non-binary low-density parity-check codes 
    Lacruz, Jesús Omar; García Herrero, Francisco Miguel; Valls Coquillat, Javier; Declercq, David (Institute of Electrical and Electronics Engineers (IEEE), 2015-01)
    A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, ...
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    Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm 
    Lacruz, Jesús O.; García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016-02-04)
    Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node processor, for high-order Galois fields higher ...
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    Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages 
    Lacruz Jucht, Jesús Omar; García Herrero, Francisco Miguel; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2015-11)
    In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged ...
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    Reliability-based iterative decoding algorithm for LDPC codes with low variable-node degree 
    Català Pérez, Joan Marc; García Herrero, Francisco Miguel; Valls Coquillat, Javier; Liu, K.; Lin, S. (Institute of Electrical and Electronics Engineers (IEEE), 2014-12)
    In this letter, a new reliability-based iterative majority-logic decoding (RBI-MLGD) algorithm that computes the extrinsic information of previous iterations of the variable node is proposed. This decoding algorithm is ...
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    Serial symbol-reliability based algorithm for decoding non-binary LDPC codes 
    García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier; Flanagan, Mark F. (Institute of Electrical and Electronics Engineers (IEEE), 2012-06)
    A symbol-reliability based decoding algorithm with serial schedule for non-binary low-density parity-check (LDPC) codes is presented. Performance results, together with implementation complexity analysis, are provided for ...
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    Simplified trellis min-max decoder architecture for nonbinary low-density parity-check codes 
    Lacruz Jucht, Jesús Omar; García Herrero, Francisco Miguel; Declercq, David; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2015-09)
    Nonbinary low-density parity-check (NB-LDPC) codes have become an efficient alternative to their binary counterparts in different scenarios, such as moderate codeword lengths, high-order modulations, and burst error ...