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Listar por autor "Selfa Oliver, Vicent"

Mostrando ítems 1-11 de 11

A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches

Selfa-Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia (Institute of Electrical and Electronics Engineers, 2017)

[EN] Shared caches have become the common design choice in the vast majority of modern multi-core and many-core processors, since cache sharing improves throughput for a given silicon area. Sharing the cache, however, has ...
A Research-Oriented Course on Advanced Multicore Architecture

Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Selfa Oliver, Vicent; Gómez Requena, María Engracia (IEEE Computer Society, 2015-05)

Multicore processors have become ubiquitous in our real life in devices like smartphones, tablets, etc. In fact, they are present in almost all segments of the computing market, from supercomputers to embedded devices. The ...
A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies

Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Selfa-Oliver, Vicent (Elsevier, 2017)

[EN] The fast evolution of multicore processors makes it difficult for professors to offer computer architecture courses with updated contents. To deal with this shortcoming that could discourage students, the most appropriate ...
Adaptive prefetch for multicores

Selfa Oliver, Vicent (Universitat Politècnica de València, 2016-01-08)

[EN] Current multicore systems implement various hardware prefetchers since prefetching can significantly hide the huge main memory latencies. However, memory bandwidth is a scarce resource which becomes critical with ...
Adaptive Prefetching and Cache Partitioning for Multicore Processors

Selfa Oliver, Vicent (Universitat Politècnica de València, 2018-11-13)

El acceso a la memoria principal en los procesadores actuales supone un importante cuello de botella para las prestaciones, dado que los diferentes núcleos compiten por el limitado ancho de banda de memoria, agravando la ...
Critical Phase-Aware Partitioning Approach (CPA)

Pons Escat, Lucía; Selfa Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Pons Terol, Julio (Universitat Politècnica de València, 2020-05-14)

CPA is LLC (Last Level Cache) partitioning approach that performs an efficient cache space distribution among executing applications. To assign partitions (ways) of the LLC, Intel CAT is used. This policy is included in a ...
Efficient Selective Multicore Prefetching under Limited Memory Bandwidth

Selfa-Oliver, Vicent; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Gómez Requena, Crispín (Elsevier, 2018)

[EN] Current multicore systems implement multiple hardware prefetchers to tolerate long main memory latencies. However, memory bandwidth is a scarce shared resource which becomes critical with the increasing core count. ...
Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications

Pons-Escat, Lucía; Selfa, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Pons Terol, Julio (Springer, 2018-08-31)

[EN] Resource sharing is a major concern in current multicore processors. Among the shared system resources, the Last Level Cache (LLC) is one of the most critical, since destructive interference between applications ...
Mejora de prestaciones de procesadores comerciales utilizando la tecnología Intel CAT

Pons Escat, Lucía (Universitat Politècnica de València, 2018-09-06)

[ES] La compartición de recursos tiene un gran impacto en las prestaciones de los procesadores multinúcleo actuales. Entre los recursos compartidos del sistema, la memoria caché de último nivel o Last Level Cache (LLC) ...
Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

Pons-Escat, Lucía; Sahuquillo Borrás, Julio; Selfa, Vicent; Petit Martí, Salvador Vicente; Pons Terol, Julio (Institute of Electrical and Electronics Engineers, 2020-11-01)

[EN] The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, ...
Prebúsqueda adaptativa para procesadores multinúcleo

Selfa Oliver, Vicent (Universitat Politècnica de València, 2013-09-30)

El propósito de este proyecto es diseñar y evaluar mediante simulación un mecanismo dinámico de activación y desactivación de la prebúsqueda de manera independiente para cada uno de los núcleos del microprocesador. Todo ...