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Listar por autor "Ros Bardisa, Alberto"

Mostrando ítems 1-13 de 13

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

Esteve García, Albert (Universitat Politècnica de València, 2017-09-01)

Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...
Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors

Esteve García, Albert; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2016-03)

Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...
Evaluación de procesadores OoO basados en la arquitectura RISC-V

Berger López, Derek Angelo (Universitat Politècnica de València, 2020-12-11)

[ES] Debido a los múltiples simuladores de RISC-V ISA y extensiones abiertas, se realiza un estudio donde se analizan ventajas e inconvenientes de los núcleos más importantes (BOOM, Ariane, Rocket, RiskyOO,¿) haciendo ...
Extending magny-cours cache coherence

Ros Bardisa, Alberto; Cuesta Sáez, Blas Antonio; Fernández-Pascual, Ricardo; Gómez Requena, María Engracia; Acacio Sánchez, Manuel E.; Robles Martínez, Antonio; García Carrasco, José Manuel; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-05)

One cost-effective way to meet the increasing demand for larger high-performance shared-memory servers is to build clusters with off-the-shelf processors connected with low-latency point-to-point interconnections like ...
Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks

Cuesta Sáez, Blas Antonio; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2013-03)

A key aspect in the design of efficient multiprocessor systems is the cache coherence protocol. Although directory-based protocols constitute the most scalable approach, the limited size of the directory caches together ...
PS directory: a scalable multilevel directory cache for CMPs

Valls, Joan J; Ros Bardisa, Alberto; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Springer Verlag (Germany), 2015-08)

As the number of cores increases in current and future chip-multiprocessor (CMP) generations, coherence protocols must rely on novel hardware structures to scale in terms of performance, power, and area. Systems that use ...
PS-Cache: an energy-efficient cache design for chip multiprocessors

Valls, Joan J; Ros Bardisa, Alberto; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Springer Verlag (Germany), 2015-01)

Power consumption has become a major design concern in current high-performance chip multiprocessors, and this problem exacerbates with the number of core counts. A significant fraction of the total power budget is often ...
PS-Dir: A Scalable Two-Level Directory Cache

Valls, Joan J.; Ros Bardisa, Alberto; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Duato Marín, José Francisco (IEEE Computer Society, 2012)

As the number of cores increases in both incoming and future chip multiprocessors, coherence protocols must address novel hardware structures in order to scale in terms of performance, power, and area. It is well ...
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors

Ros Bardisa, Alberto; Cuesta Sáez, Blas Antonio; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (IEEE, 2013)

Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by only one thread and can be considered as private data. A lot of recent proposals leverage ...
The Tag Filter Architecture: An energy-efficient cache and directory design

Valls, Joan; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Elsevier, 2017)

[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major design concern that aggravates with the current trend of increasing the core count. A significant fraction of the total power ...
TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs

Esteve Garcia, Albert; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers, 2017-08-01)

[EN] Recent proposals are based on classifying memory accesses into private or shared in order to process private accesses more efficiently and reduce coherence overhead. The classification mechanisms previously proposed ...
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction

Esteve Garcia, Albert; Ros Bardisa, Alberto; Robles Martínez, Antonio; Gómez Requena, María Engracia (Institute of Electrical and Electronics Engineers, 2018)

[EN] Discerning the private or shared condition of the data accessed by the applications is an increasingly decisive approach to achieving efficiency and scalability in multi- and many-core systems. Since most memory ...
Way Combination for an Adaptive and Scalable Coherence Directory

Titos-Gil, Rubén; Flores, Antonio; Fernández-Pascual, Ricardo; Ros, Alberto; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Acacio, Manuel E. (Institute of Electrical and Electronics Engineers, 2019-11)

[EN] This manuscript opens the way to a new class of coherence directory structures that are based on the brand-new concept of way combining. A Way-Combining Directory (WC-dir) builds on a typical sparse directory but ...