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Listar por autor "Lodde, Mario"

Mostrando ítems 1-5 de 5

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Built-in fast gather control network for efficient support of coherence protocols

Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José (Institution of Engineering and Technology (IET), 2013-03)

[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
Efficient built-in NoC support for gather operations in invalidation-based coherence protocols

Lodde, Mario (Universitat Politècnica de València, 2014-11-28)

[EN] A dedicated control network is used to transmit acknowledgement messages generated by the coherence protocol, thus reducing the traffic in the regular NoC and improving the overall system performance
Runtime home mapping for effective memory resource usage

Lodde, Mario; Flich Cardo, José (Elsevier, 2014-06)

In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poor efficiency since a block may be mapped ...
Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

Lodde, Mario (Universitat Politècnica de València, 2014-02-04)

La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo ...