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Listar por autor "Puche Lara, José"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por autor "Puche Lara, José"

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    Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework 
    Puche Lara, José; Lechago Buendía, Sergio; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (IEEE, 2016)
    Photonic interconnects are a promising solution for the so-called communication bottleneck in current Chip Multiprocessor (CMPs) architectures. This technology presents an inherent low-latency and power consumption almost ...
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    An efficient cache flat storage organization for multithreaded workloads for low power processors 
    Puche, José; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Elsevier, 2020-09)
    [EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the faster and smaller L1 level to the slower and larger L3 level. This approach has been demonstrated to be effective in high ...
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    Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources 
    Pons-Escat, Lucía; Feliu-Pérez, Josué; Puche-Lara, José; Huang, Chaoyi; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Elsevier, 2022-06)
    [EN] Multithreaded latency-critical applications represent an important subset of workloads running on public cloud systems. Most of these systems deploy powerful computing servers including Intel Hyper-Threading processors. ...
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    Estudio de la viabilidad de una red híbrida foto-eléctrica 
    Puche Lara, José (Universitat Politècnica de València, 2015-09-29)
    [ES] Recientemente, las redes ópticas han aparecido como una alternativa a las redes eléctricas dentro del chip, por su bajo consumo, alto ancho de banda, y latencia independiente de la distancia. Sin embargo, el coste ...
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    FOS: a low-power cache organization for multicores 
    Puche-Lara, José; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Springer-Verlag, 2019-10)
    [EN] The cache hierarchy of current multicore processors typically consists of one or two levels of private caches per core and a large shared last-level cache. This approach incurs area and energy wasting due to oversizing ...
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    Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors 
    Puche Lara, José (Universitat Politècnica de València, 2021-04-13)
    [ES] Los procesadores multinúcleo actuales cuentan con recursos compartidos entre los diferentes núcleos. Dos de estos recursos compartidos, la cache de último nivel y el ancho de banda de memoria principal, pueden convertirse ...
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    Understanding Cloud Workloads Performance in a Production like Environment 
    Pons-Escat, Lucía; Feliu-Pérez, Josué; Puche, José; Huang, Chaoyi; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Sahuquillo, Julio (Cornell University, 2020-10)
    [EN] Understanding inter-VM interference is of paramount importance to provide a sound knowledge and understand where performance degradation comes from in the current public cloud. With this aim, this paper devises a ...