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Listar por autor "Tuzov, Ilya"

Mostrando ítems 1-6 de 6

BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes

Tuzov, Ilya; de-Andrés-Martínez, David; Ruiz, Juan Carlos; Hernández Luz, Carles (IEEE, 2023-04-19)

[EN] FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs and prototypes. Existing FFI tools make use of Xilinx essential bits technology to locate ...
Dependability-driven Strategies to Improve the Design and Verification of Safety-Critical HDL-based Embedded Systems

Tuzov, Ilya (Universitat Politècnica de València, 2021-01-25)

[ES] La utilización de sistemas empotrados en cada vez más ámbitos de aplicación está llevando a que su diseño deba enfrentarse a mayores requisitos de rendimiento, consumo de energía y área (PPA). Asimismo, su utilización ...
Improving the Robustness of Redundant Execution with Register File Randomization

Tuzov, Ilya; Andreu, Pablo; Medina, Laura; Picornell-Sanjuan, Tomás; Robles Martínez, Antonio; López Rodríguez, Pedro Juan; Flich Cardo, José; Hernández Luz, Carles (IEEE, 2021-11-04)

[EN] Staggered Redundant execution (SRE) is a fault-tolerance mechanism that has been widely deployed in the context of safety-critical applications. SRE not only protects the system in the presence of faults but also helps ...
Reversing FPGA Architectures for Speeding up Fault Injection: does it pay?

Tuzov, Ilya; de-Andrés-Martínez, David; Ruiz, Juan Carlos (IEEE, 2022-09-15)

[EN] Although initially considered for fast system prototyping, Field Programmable Gate Arrays (FPGAs) are gaining interest for implementing final products thanks to their inherent reconfiguration capabilities. As they are ...
Simulating the effects of logic faults in implementation-level VITAL-compliant models

Tuzov, Ilya; de-Andrés-Martínez, David; Ruiz, Juan Carlos (Springer-Verlag, 2019-02)

[EN] Simulation-based fault injection is a well-known technique to assess the dependability of hardware designs specified using hardware description languages (HDL). Although logic faults are usually introduced in models ...
Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study

Tuzov, Ilya; Andrés, David de; Ruiz, Juan Carlos (Elsevier, 2018)

[EN] The steady growth in complexity of FPGAs has led designers to rely more and more on manufacturers¿ and third parties¿ design tools to meet their implementation goals. However, as modern synthesis tools provide a myriad ...