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Listar por autor "Andreu Cerezo, Pablo"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por autor "Andreu Cerezo, Pablo"

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    Design and verification of a Systolic Array Multiplier 
    Andreu Cerezo, Pablo (Universitat Politècnica de València, 2020-07-30)
    [EN] Artificial intelligence aims to solve much of the problems of the contemporary society that we live in. But, in order for it to be ever so prevalent, the development of efficient inference-specific chips is needed, ...
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    Hashing ATD Tags for Low-Overhead Safe Contention Monitoring 
    Andreu-Cerezo, Pablo; López Rodríguez, Pedro Juan; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers, 2024-12)
    [EN] Increasing the performance of safety-critical systems via introducing multicore processors is becoming the norm. However, when multiple cores access a shared cache, inter-core evictions become a relevant source of ...
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    Improving the Robustness of Redundant Execution with Register File Randomization 
    Tuzov, Ilya; Andreu, Pablo; Medina, Laura; Picornell-Sanjuan, Tomás; Robles Martínez, Antonio; López Rodríguez, Pedro Juan; Flich Cardo, José; Hernández Luz, Carles (IEEE, 2021-11-04)
    [EN] Staggered Redundant execution (SRE) is a fault-tolerance mechanism that has been widely deployed in the context of safety-critical applications. SRE not only protects the system in the presence of faults but also helps ...
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    Measuring and Controlling Multicore Contention in a RISC-V System-on-Chip 
    Andreu Cerezo, Pablo (Universitat Politècnica de València, 2021-09-30)
    [ES] Los procesadores multinúcleo empezaron una revolución en el cómputo moderno cuando fueron introducidos en el espacio de cómputo comercial y de consumidor. Estos procesadores multinúcleo presentaban un aumento significativo ...