- -

Listar por Entidad UPV "Universitat Politècnica de València. Grupo de Arquitecturas Paralelas"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por Entidad UPV "Universitat Politècnica de València. Grupo de Arquitecturas Paralelas"

Ordenar por:Orden:Resultados:

  • Icon
    Built-in fast gather control network for efficient support of coherence protocols 
    Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José (Institution of Engineering and Technology (IET), 2013-03)
    [EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
  • Icon
    Characterizing the impact of process variation on 45 nm NoC-based CMPs 
    Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-05)
    [EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor ...
  • Icon
    Cost-efficient on-chip routing implementations for CMP and MPSoC systems 
    Rodrigo Mocholí, Samuel; Flich Cardo, José; Roca Pérez, Antoni; Medardoni, Simone; Bertozzi, Davide; Camacho Villanueva, Jesús; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-04)
    [EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...
  • Icon
    Critical Phase-Aware Partitioning Approach (CPA) 
    Pons Escat, Lucía; Selfa Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Pons Terol, Julio (Universitat Politècnica de València, 2020-05-14)
    CPA is LLC (Last Level Cache) partitioning approach that performs an efficient cache space distribution among executing applications. To assign partitions (ways) of the LLC, Intel CAT is used. This policy is included in a ...
  • thumb
    InfiniBand verbs optimizations for remote GPU virtualization 
    Reaño González, Carlos; Silla Jiménez, Federico (IEEE, 2015-09-08)
    The use of InfiniBand networks to interconnect high performance computing clusters has considerably increased during the last years. So much so that the majority of the supercomputers included in the TOP500 list either ...
  • Icon
    Network-on-Chip Virtualization in Chip-Multiprocessor Systems 
    Triviño, Francisco; Sanchez Garcia, Jose Luis; Alfaro, Francisco J.; Flich Cardo, José (Elsevier, 2012-03)
    [EN] It is expected that Chip Multiprocessor Systems (CMPs) will contain more and more cores in every new generation. However, applications for these systems do not scale at the same pace. In order to obtain a good CMP ...
  • thumb
    On the design of a demo for exhibiting rCUDA 
    Reaño González, Carlos; Pérez López, Ferran; Silla Jiménez, Federico (IEEE, 2015-05-04)
    CUDA is a technology developed by NVIDIA which provides a parallel computing platform and programming model for NVIDIA GPUs and compatible ones. It takes benefit from the enormous parallel processing power of GPUs in ...