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Listar por palabra clave "Cache coherence"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "Cache coherence"

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    Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors 
    Esteve García, Albert (Universitat Politècnica de València, 2017-09-01)
    Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...
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    Efficient and scalable starvation prevention mechanism for token coherence 
    Cuesta Sáez, Blas Antonio; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-10)
    [EN] Token Coherence is a cache coherence protocol that simultaneously captures the best attributes of the traditional approximations to coherence: direct communication between processors (like snooping-based protocols) ...
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    Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors 
    Esteve García, Albert; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2016-03)
    Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...
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    Extending magny-cours cache coherence 
    Ros Bardisa, Alberto; Cuesta Sáez, Blas Antonio; Fernández-Pascual, Ricardo; Gómez Requena, María Engracia; Acacio Sánchez, Manuel E.; Robles Martínez, Antonio; García Carrasco, José Manuel; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-05)
    One cost-effective way to meet the increasing demand for larger high-performance shared-memory servers is to build clusters with off-the-shelf processors connected with low-latency point-to-point interconnections like ...
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    Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks 
    Cuesta Sáez, Blas Antonio; Ros Bardisa, Alberto; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2013-03)
    A key aspect in the design of efficient multiprocessor systems is the cache coherence protocol. Although directory-based protocols constitute the most scalable approach, the limited size of the directory caches together ...
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    PS-Dir: A Scalable Two-Level Directory Cache 
    Valls, Joan J.; Ros Bardisa, Alberto; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia; Duato Marín, José Francisco (IEEE Computer Society, 2012)
    As the number of cores increases in both incoming and future chip multiprocessors, coherence protocols must address novel hardware structures in order to scale in terms of performance, power, and area. It is well ...
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    Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors 
    Ros Bardisa, Alberto; Cuesta Sáez, Blas Antonio; Gómez Requena, María Engracia; Robles Martínez, Antonio; Duato Marín, José Francisco (IEEE, 2013)
    Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by only one thread and can be considered as private data. A lot of recent proposals leverage ...
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    Way Combination for an Adaptive and Scalable Coherence Directory 
    Titos-Gil, Rubén; Flores, Antonio; Fernández-Pascual, Ricardo; Ros, Alberto; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Acacio, Manuel E. (Institute of Electrical and Electronics Engineers, 2019-11)
    [EN] This manuscript opens the way to a new class of coherence directory structures that are based on the brand-new concept of way combining. A Way-Combining Directory (WC-dir) builds on a typical sparse directory but ...