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Listar por palabra clave "Cache hierarchy"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "Cache hierarchy"

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    An efficient cache flat storage organization for multithreaded workloads for low power processors 
    Puche, José; Petit Martí, Salvador Vicente; Gómez Requena, María Engracia; Sahuquillo Borrás, Julio (Elsevier, 2020-09)
    [EN] The cache hierarchy of current multicores typically consists of three levels, ranging from the faster and smaller L1 level to the slower and larger L3 level. This approach has been demonstrated to be effective in high ...
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    Cache-Hierarchy contention-aware scheduling in CMPs 
    Feliu Pérez, Josué; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2014-03)
    To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are ...
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    Efficient built-in NoC support for gather operations in invalidation-based coherence protocols 
    Lodde, Mario (Universitat Politècnica de València, 2014-11-28)
    [EN] A dedicated control network is used to transmit acknowledgement messages generated by the coherence protocol, thus reducing the traffic in the regular NoC and improving the overall system performance
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    Evaluación de la jerarquía de cache en procesadores multinúcleo 
    Vivas Vivas, Julio Antonio (Universitat Politècnica de València, 2015-03-26)
    [ES] Este proyecto se centra en la evaluación de diferentes jerarquías de cache reales (basadas en los últimos diseños de Intel) en procesadores multinúcleo. Los estudios se realizan mediante el simulador Multi2Sim para ...
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    FOS: a low-power cache organization for multicores 
    Puche-Lara, José; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Springer-Verlag, 2019-10)
    [EN] The cache hierarchy of current multicore processors typically consists of one or two levels of private caches per core and a large shared last-level cache. This approach incurs area and energy wasting due to oversizing ...
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    Runtime home mapping for effective memory resource usage 
    Lodde, Mario; Flich Cardo, José (Elsevier, 2014-06)
    In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poor efficiency since a block may be mapped ...
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    Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors 
    Lodde, Mario (Universitat Politècnica de València, 2014-02-04)
    La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo ...
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    Understanding cache hierarchy contention in CMPs to improve job scheduling 
    Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (IEEE, 2012-05-21)
    In order to improve CMP performance, recent research has focused on scheduling to mitigate contention produced by the limited memory bandwidth. Nowadays, commercial CMPs implement multi-level cache hierarchies where last ...