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Listar por palabra clave "Cache memories"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "Cache memories"

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    Design of Hybrid Second-Level Caches 
    Valero Bresó, Alejandro; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; López Rodríguez, Pedro Juan; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2015-07)
    In recent years, embedded dynamic random-access memory (eDRAM) technology has been implemented in last-level caches due to its low leakage energy consumption and high density. However, the fact that eDRAM presents slower ...
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    Enhancing the L1 Data Cache Design to Mitigate HCI 
    Valero Bresó, Alejandro; Miralaei, Negar; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Jones, Timothy M. (Institute of Electrical and Electronics Engineers (IEEE), 2016-07)
    [EN] Over the lifetime of a microprocessor, the Hot Carrier Injection (HCI) phenomenon degrades the threshold voltage, which causes slower transistor switching and eventually results in timing violations and faulty operation. ...
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    Hybrid caches: design and data management 
    Valero Bresó, Alejandro (Editorial Universitat Politècnica de València, 2013-10-07)
    Cache memories have been usually implemented with Static Random-Access Memory (SRAM) technology since it is the fastest electronic memory technology. However, this technology consumes a high amount of leakage currents, ...
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    Interference Analysis and Resource Management in Server Processors: from HPC to Cloud Computing 
    Pons Escat, Lucía (Universitat Politècnica de València, 2023-09-01)
    [ES] Una de las principales preocupaciones de los centros de datos actuales es maximizar la utilización de los servidores. En cada servidor se ejecutan simultáneamente varias aplicaciones para aumentar la eficiencia de los ...
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    On Microarchitectural Mechanisms for Cache Wearout Reduction 
    Valero Bresó, Alejandro; Miralaei, Negar; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Jones, Timothy M. (Institute of Electrical and Electronics Engineers, 2017-03)
    [EN] Hot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation ...
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    Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance 
    Pons-Escat, Lucía; Sahuquillo Borrás, Julio; Selfa, Vicent; Petit Martí, Salvador Vicente; Pons Terol, Julio (Institute of Electrical and Electronics Engineers, 2020-11-01)
    [EN] The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, ...
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    PS-Cache: an energy-efficient cache design for chip multiprocessors 
    Valls, Joan J; Ros Bardisa, Alberto; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Springer Verlag (Germany), 2015-01)
    Power consumption has become a major design concern in current high-performance chip multiprocessors, and this problem exacerbates with the number of core counts. A significant fraction of the total power budget is often ...