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PS-Cache: an energy-efficient cache design for chip multiprocessors

Valls, Joan J; Ros Bardisa, Alberto; Sahuquillo Borrás, Julio; Gómez Requena, María Engracia (Springer Verlag (Germany), 2015-01)

Power consumption has become a major design concern in current high-performance chip multiprocessors, and this problem exacerbates with the number of core counts. A significant fraction of the total power budget is often ...
Runtime home mapping for effective memory resource usage

Lodde, Mario; Flich Cardo, José (Elsevier, 2014-06)

In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poor efficiency since a block may be mapped ...
Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

Lodde, Mario (Universitat Politècnica de València, 2014-02-04)

La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo ...

Mostrando ítems 1-3 de 3