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Listar por palabra clave "Error correction codes"

Mostrando ítems 1-7 de 7

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

Gil Tomás, Daniel Antonio; Saiz-Adalid, Luis-J.; Gracia-Morán, Joaquín; Baraza-Calvo, Juan-Carlos; Gil, Pedro (Institute of Electrical and Electronics Engineers, 2024)

[EN] MBU is an increasing challenge in SRAM memory, due to the chip's large area of SRAM, and supply power scaling applied to reduce static consumption. Powerful ECCs can cope with random MBUs, but at the expense of complex ...
A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán, Joaquín; Saiz-Adalid, Luis-J.; Baraza-Calvo, Juan-Carlos; Gil Tomás, Daniel Antonio; Gil, Pedro (Institute of Electrical and Electronics Engineers, 2024-05)

[EN] With the integration scale level reached in CMOS technology, memory systems provide a great storage capacity, but at the price of an augment in their fault rate. In this way, the probability of experiencing Single ...
Diseño de una estación meteorológica basada en Arduino con propiedades de tolerancia a fallos en la memoria del microprocesador

Sammut Rodríguez, Tomás Luc (Universitat Politècnica de València, 2024-09-09)

[ES] En este Trabajo de Fin de Grado se ha diseñado y construido una estación meteorológica formada por una placa Arduino Mega 2560, un sensor de temperatura y humedad DHT11, un LED RGB, dos LEDs, uno rojo y otro verde ...
Generación automática de códigos de corrección de errores en VHDL a partir de su matriz de paridad H

Morilla Rodriguez, Cristina (Universitat Politècnica de València, 2021-09-13)

[CA] Els sistemes d’informació poden patir danys que modifiquen el missatge que es pretén transmetre, en un moment donat, per causes molt diverses. Com a solució, els sistemes tolerants a fallades, per mitjà dels codis ...
Multiple-vote symbol flipping decoder for non-binary LDPC codes

García Herrero, Francisco Miguel; Li, Erbao; Declercq, David; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2014-11)

A multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering ...
Non-binary LDPC decoder based on simplified enhanced generalized bit flipping algorithm

García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2014-06)

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB ...
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes

Valls Coquillat, Javier; García-Herrero, Francisco; Raveendran, Nithin; Vasic, Bane (Institute of Electrical and Electronics Engineers, 2021)

[EN] Quantum processors need to improve their reliability to scale up the number of qubits and increase the number of algorithms that can execute. To reduce the logical error rate of the quantum systems, the use of error ...