[EN] Networks-on-chip need to survive to manufacturing faults in order to sustain yield. An effective testing and
configuration strategy however implies two opposite requirements. One one hand, a fast and scalable ...
Bermúdez Garzón, Diego Fernando; Gómez Requena, Crispín; Gómez Requena, María Engracia; López Rodríguez, Pedro Juan; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2016-04)
On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are ...
Díaz Santos, Juan Ramón(Universitat Politècnica de València, 2016-04-05)
[EN] This dissertation addresses the problem of multimedia delivery over multi-hop ad hoc wireless networks, and especially over wireless sensor networks. Due to their characteristics of low power consumption, low processing ...
Cobos Tello, Gabriel(Universitat Politècnica de València, 2019-09-18)
[ES] Este proyecto será una disertación sobre el campo de la tolerancia a fallos aplicada a aplicaciones espaciales basadas en FPGA. En este artículo se discutirá la necesidad de tales técnicas al proporcionar información ...
Hernández Luz, Carles; Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco(Institute of Electrical and Electronics Engineers (IEEE), 2011-12)
[EN] Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors
(CMPs). As the number of integrated cores in the chip increases the access to external memory becomes ...