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Listar por palabra clave "Hardware architecture"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "Hardware architecture"

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    Diseño de AUV.Arquitectura de hardware y software 
    Martínez, Alain; Rodriguez, Yidier; Hernández, Luis; Guerra, Carlos; Lemus, Jorge; Sahli, Hichem (Universitat Politècnica de València, 2013-07-09)
    [ES] El presente documento discute la estrategia bajo la que fueron concebidas la arquitectura de hardware y software para el prototipo de vehículo autónomo: HRC-AUV, así como la selección de los elementos fundamentales ...
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    Hardware architecture of a gaussian noise generator based on inversion method 
    Gutiérrez, Roberto G.; Torres Carot, Vicente; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2012-08)
    In this brief, we present a hardware-based Gaussian noise generator (GNG) with low hardware cost, high generation rate, and high Gaussian tail accuracy. The proposed generator is based on a piecewise polynomial approximation ...
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    Hardware Architecture of a QAM Receiver for Short-Range Optical Communications 
    Valls Coquillat, Javier; Torres Carot, Vicente; Pérez Pascual, Mª Asunción; Almenar Terre, Vicenç (Institute of Electrical and Electronics Engineers, 2023-01-15)
    [EN] Short-reach optical fiber communications systems aim to achieve high throughput, in the order of tens of Gbps. The implementation of these high-speed systems requires parallel processing, which makes low-complexity ...
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    Non-binary LDPC decoder based on simplified enhanced generalized bit flipping algorithm 
    García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2014-06)
    A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB ...