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Listar por palabra clave "LDPC"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "LDPC"

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    A GPU implementation of an iterative receiver for energy saving MIMO ID-BICM systems 
    Ramiro Sánchez, Carla; Simarro Haro, Mª de los Angeles; Martínez Zaldívar, Francisco José; Vidal Maciá, Antonio Manuel; Gonzalez, Alberto (Springer Verlag, 2014-11)
    Iterative detection and decoding in communication systems with multiple transmitter and receiver antennas suffer from a significant increase in the computational cost and energy consumption. Nowadays, application of specific ...
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    Architectures for soft-decision decoding of non-binary codes 
    García Herrero, Francisco Miguel (Universitat Politècnica de València, 2013-11-19)
    En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los ...
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    Bit-Interleaved Coded Modulation (BICM) for ATSC 3.0 
    Michael, Lachlan; Gómez Barquero, David (Institute of Electrical and Electronics Engineers (IEEE), 2016-03)
    In this paper, we summarize and expound upon the choices made for the bit-interleaved coded modulation (BICM) part of the next-generation terrestrial broadcast standard known as ATSC 3.0. The structure of the ATSC 3.0 BICM ...
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    Design and implementation of decoders for error correction in high-speed communication systems 
    Català Pérez, Joan Marc (Universitat Politècnica de València, 2017-09-01)
    This thesis is focused on the design and implementation of binary low-density parity-check (LDPC) code decoders for high-speed modern communication systems. The basic of LDPC codes and the performance and bottlenecks, in ...
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    Diseño e implementación en FPGA de un decodificador de códigos LDPC con secuenciación por capas 
    Mascarell Català, Ferran (Universitat Politècnica de València, 2013-11-27)
    The Low-Density Parity-Check codes (LDPC) have been included in most of the comunicaction standars mainly due to two facts. First, their error correction capability is very high, making the data transmision rate close ...
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    Implementación en FPGA de un codificador de alta velocidad para códigos LDPC quasi cíclicos 
    Correcher Soriano, José (Universitat Politècnica de València, 2013-06-20)
    [ES] Los códigos LDPC son códigos de bloques lineales caracterizados por una matriz de comprobación de paridad dispersa. Su capacidad de corrección consigue aproximarse al límite establecido por Shannon, esto hace que ...
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    Parallel Implementation Strategies for MIMO ID-BICM Systems 
    Simarro Haro, Mª de los Angeles; Ramiro Sánchez, Carla; Martínez Zaldívar, Francisco José; Vidal Maciá, Antonio Manuel; González Téllez, Alberto; Piñero Sipán, María Gemma; García Mollá, Víctor Manuel (2013)
    [EN] One of the current techniques proposed for multiple transmit and receive antennas wireless communication systems is the use of error control coding and iterative detection and decoding at the receiver. These sophisticated ...
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    Performance evaluation of AL-FEC LDPC codes for push content applications in wireless unidirectional environments 
    De Fez Lava, Ismael; Fraile Gil, Francisco; Belda Ortega, Román; Guerri Cebollada, Juan Carlos (Springer Verlag (Germany), 2012-10)
    FEC (Forward Error Correction) mechanisms improve IP content transmission reliability through the recovery of packets lost in transmission. Opposite to ARQ (Automatic Repeat Request), FEC mechanisms are especially suited ...
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    Tridimensional block multiword LDPC decoding on GPUs 
    Martínez Zaldívar, Francisco José; Vidal Maciá, Antonio Manuel; González Salvador, Alberto; Almenar Terré, Vicenç (Springer Verlag (Germany), 2011-12)
    [EN] In this paper, we describe a parallel algorithm for LDPC (Low Density Parity Check codes) decoding on a GPU (Graphics Processing Unit) using CUDA (Compute Unified Device Architecture). The strategy of the kernel grid ...