Valero Bresó, Alejandro; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; López Rodríguez, Pedro Juan; Duato Marín, José Francisco(Association for Computing Machinery (ACM), 2012)
Memory latency has become an important performance bottleneck in current microprocessors. This problem aggravates as the number of cores sharing the same memory controller increases. To palliate this problem, a common ...
Valero Bresó, Alejandro; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco(ACM, 2013-06)
This work introduces a novel refresh mechanism that leverages
reuse information to decide which blocks should be refreshed in an
energy-aware eDRAM last-level cache. Experimental results show
that, compared to a ...
Valero Bresó, Alejandro(Editorial Universitat Politècnica de València, 2013-10-07)
Cache memories have been usually implemented with Static Random-Access Memory
(SRAM) technology since it is the fastest electronic memory technology. However, this
technology consumes a high amount of leakage currents, ...