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Listar por palabra clave "Memory hierarchy"

Mostrando ítems 1-8 de 8

Adaptive prefetch for multicores

Selfa Oliver, Vicent (Universitat Politècnica de València, 2016-01-08)

[EN] Current multicore systems implement various hardware prefetchers since prefetching can significantly hide the huge main memory latencies. However, memory bandwidth is a scarce resource which becomes critical with ...
Critical Phase-Aware Partitioning Approach (CPA)

Pons Escat, Lucía; Selfa Oliver, Vicent; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Pons Terol, Julio (Universitat Politècnica de València, 2020-05-14)

CPA is LLC (Last Level Cache) partitioning approach that performs an efficient cache space distribution among executing applications. To assign partitions (ways) of the LLC, Intel CAT is used. This policy is included in a ...
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance

Candel-Margaix, Francisco; Valero Bresó, Alejandro; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio (Institute of Electrical and Electronics Engineers, 2019-10-01)

[EN] To support the massive amount of memory accesses that GPGPU applications generate, GPU memory hierarchies are becoming more and more complex, and the Last Level Cache (LLC) size considerably increases each GPU generation. ...
Interference Analysis and Resource Management in Server Processors: from HPC to Cloud Computing

Pons Escat, Lucía (Universitat Politècnica de València, 2023-09-01)

[ES] Una de las principales preocupaciones de los centros de datos actuales es maximizar la utilización de los servidores. En cada servidor se ejecutan simultáneamente varias aplicaciones para aumentar la eficiencia de los ...
LUT saving in embedded FPGAs for cache locking in real-time systems

Martí Campoy, Antonio; Rodríguez Ballester, Francisco; Ors Carot, Rafael (2013)

[EN] In recent years, cache locking have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular ...
Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors

Puche Lara, José (Universitat Politècnica de València, 2021-04-13)

[ES] Los procesadores multinúcleo actuales cuentan con recursos compartidos entre los diferentes núcleos. Dos de estos recursos compartidos, la cache de último nivel y el ancho de banda de memoria principal, pueden convertirse ...
Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance

Pons-Escat, Lucía; Sahuquillo Borrás, Julio; Selfa, Vicent; Petit Martí, Salvador Vicente; Pons Terol, Julio (Institute of Electrical and Electronics Engineers, 2020-11-01)

[EN] The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The inter-application interference at this shared resource, ...
Planificación de tareas considerando la contención en la jerarquía de memoria de procesadores multinúcleo

Feliu Pérez, Josué (Universitat Politècnica de València, 2013-02-25)

[ES] Con el objetivo de mejorar el rendimiento de los CMPs, parte de la investigación reciente se ha centrado en la planificación de procesos para limitar la contención provocada por el limitado ancho de banda. Hoy en dia, ...