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Listar por palabra clave "Multicore"

Mostrando ítems 1-20 de 28

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Addressing fairness in SMT multicores with a progress-aware scheduler

Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco (IEEE, 2015-05-25)

Current SMT (simultaneous multithreading) processors co-schedule jobs on the same core, thus sharing core resources like L1 caches. In SMT multicores, threads also compete among themselves for uncore resources like the LLC ...
Algoritmos de detección y filtrado de imágenes para arquitecturas multicore y manycore

Sánchez Cervantes, María Guadalupe (Universitat Politècnica de València, 2013-05-15)

En esta tesis se aborda la eliminaci'on de ruido impulsivo, gaussiano y speckle en im'agenes a color y en escala de gises. Como caso particular se puede mencionar la eliminaci'on de ruido en im'agenes m'edicas. Algunos ...
Análisis y evaluación de politicas de planificación en sistemas multicore

Martínez Mas, Andrés (Universitat Politècnica de València, 2015-06-26)

[EN] This project is a study of scheduling policies of systems with temporal restrictions on partitioned systems in multicore architectures. For this study it is taken as a point of departure a system with partitions, where ...
Automatic routine tuning to represent landform attributes on multicore and multi-GPU systems

DO CARMO BORATTO, MURILO; Alonso-Jordá, Pedro; Giménez Cánovas, Domingo; Barreto, Marcos (Springer Verlag (Germany), 2014-11)

Auto-tuning techniques have been used in the design of routines in recent years. The goal is to develop routines which automatically adapt to the conditions of the computational system in such a way that efficient executions ...
Automatic Tuning to Performance Modelling of Matrix Polynomials on Multicore and Multi-GPU Systems

Boratto, Murilo; Alonso-Jordá, Pedro; Gimenez, Domingo; Lastovetsky, Alexey (Springer-Verlag, 2017-01)

[EN] Automatic tuning methodologies have been used in the design of routines in recent years. The goal of these methodologies is to develop routines which automatically adapt to the conditions of the underlying computational ...
Desarrollo de un Procesador de Altas Prestaciones para una Arquitectura Multinúcleo en FPGA #2

Picornell Sanjuan, Tomás (Universitat Politècnica de València, 2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...
Desarrollo de un procesador de altas prestaciones para una arquitectura multinúcleo en FPGAs #1

Guaita Masiá, Francisco (Universitat Politècnica de València, 2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...
Desarrollo de un Procesador de Altas Prestaciones para una Arquitectura Multinúcleo en FPGAs #3

Lozano Torres, Raúl (Universitat Politècnica de València, 2015-07-31)

[ES] En este trabajo se diseña e implementa un procesador con ejecución fuera de orden siguiendo como modelo el algoritmo de Tomasulo. El procesador es reconfigurable y permite tanto la instanciación de un número variable ...
Development of a Highly Capable Processor for a Multicore Architecture on FPGAs #4

Holland, Mark Antony (Universitat Politècnica de València, 2015-07-31)

[EN] This project involves the design and implementation of a processor with outof-order execution using the Tomasulo algorithm. The processor is configurable, allowing a variable number of resources and functional units. ...
Diseño e implementación de software paralelo para tratamiento de datos en memoria masiva

San Juan Sebastián, Pablo (Universitat Politècnica de València, 2015-06-25)

[EN] This work focuses on designing and coding an out-of-core algorithm to solve the cholesky decomposition over a multicore machine.
Diseño e implementación del sistema de excepciones en un procesador para un sistema multicore en FPGAs

Rocher González, José Manuel (Universitat Politècnica de València, 2014-09-23)

En este trabajo se implementa el sistema de excepciones para un procesador escalar con arquitectura MIPS. El procesador se ha programado utilizando el lenguaje de descripción hardware Verilog y ha sido implementado sobre ...
Dynamic Power-Aware Techniques for Real-Time Multicore Embedded Systems

March Cabrelles, José Luis (Editorial Universitat Politècnica de València, 2015-03-30)

The continuous shrink of transistor sizes has allowed more complex and powerful devices to be implemented in the same area, which provides new capabilities and functionalities. However, this complexity increase comes ...
Exploring Hybrid Parallel Systems for Probabilistic Record Linkage

Boratto, Murilo; Alonso-Jordá, Pedro; Pinto, Clicia; Melo, Pedro; Barreto, Marcos; Denaxas, Spiros (Springer-Verlag, 2019-03)

[EN] Record linkage is a technique widely used to gather data stored in disparate data sources that presumably pertain to the same real world entity. This integration can be done deterministically or probabilistically, ...
Hardware resources contention-aware scheduling of hard real-time multiprocessor systems

Aceituno-Peinado, José María; Guasque Ortega, Ana; Balbastre, Patricia; Simó Ten, José Enrique; Crespo, Alfons (Elsevier, 2021-09)

[EN] In hard real-time embedded systems, switching to multicores is a step that most application domains delay asmuch as possible. This is mainly due to the number of sources of indeterminism, which mainly involve ...
Hashing ATD Tags for Low-Overhead Safe Contention Monitoring

Andreu-Cerezo, Pablo; López Rodríguez, Pedro Juan; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers, 2024-12)

[EN] Increasing the performance of safety-critical systems via introducing multicore processors is becoming the norm. However, when multiple cores access a shared cache, inter-core evictions become a relevant source of ...
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

Picornell-Sanjuan, Tomás; Flich Cardo, José; Duato Marín, José Francisco; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers, 2020)

[EN] The need for increasing the performance of critical real-time embedded systems pushes the industry to adopt complex multi-core processor designs with embedded networks-on-chip. In this paper we present hp-DCFNoC, a ...
Improving the performance of water distribution systems’ simulation on multicore systems

Alvarruiz Bermejo, Fernando; Martínez Alzamora, Fernando; Vidal Maciá, Antonio Manuel (Springer, 2016-01-18)

Hydraulic solvers for the simulation of flows and pressures in water distribution systems (WDS) are used extensively, and their computational performance is key when considering optimization problems. This paper presents ...
Integrating multicore awareness functions into distribution middleware for improving performance of distributed audio surveillance

Garcia Valls, Maria Soledad (Elsevier Applied Science., 2019-06)

[EN] This paper describes an approach to improve the performance of the distributed audio-processing functions for audio surveillance systems. In order to increase portability, current distributed audio-processing uses ...
Interference-Aware Schedulability Analysis and Task Allocation for Multicore Hard Real-Time Systems

Aceituno-Peinado, José María; Guasque Ortega, Ana; Balbastre, Patricia; Simó Ten, José Enrique; Crespo, Alfons (MDPI AG, 2022-05)

[EN] There has been a trend towards using multicore platforms for real-time embedded systems due to their high computing performance. In the scheduling of a multicore hard real-time system, there are interference delays ...
Modelos Paralelos para la Resolución de Problemas de Ingeniería Agrícola

DO CARMO BORATTO, MURILO (Universitat Politècnica de València, 2015-03-31)

El presente trabajo se inscribe en el campo de la computación paralela y, más en concreto, en el desarrollo y utilización de modelos computacionales en arquitecturas paralelas heterogéneas para la resolución de ...