Herraiz Calatayud, María(Universitat Politècnica de València, 2019-10-09)
[ES] La Metodología de Verificación Universal (UVM) es una metodología estandarizada para la verificación de diseños de circuitos integrados. Se basa en una extensa biblioteca de clases escritas en SystemVerilog a partir ...
Albanese, Angela A.; Bonet Solves, José Antonio; Ricker, Werner J.(Springer-Verlag, 2019-02)
[EN] The Banach sequence spaces ces(p) are generated in a specified way via the classical spaces p,1<p<. For each pair 1<p,q< the (p,q)-multiplier operators from ces(p) into ces(q) are known. We determine precisely which ...
Bonet Solves, José Antonio; RICKER, WERNER(Springer-Verlag, 2020-03)
[EN] The discrete Cesaro (Banach) sequence spaces ces(r),1<r<infinity, have been thoroughly investigated for over 45 years. Not so for their dual spaces d(s) approximately equal to (ces(r))', which are somewhat unwieldy. ...