- -

Listar por palabra clave "Networks-on-chip"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "Networks-on-chip"

Ordenar por:Orden:Resultados:

  • Icon
    A communication-driven routing technique for application-specific NoCs 
    Tornero, Rafael; Orduña Huertas, Juan Manuel; Mejia, Andres; Flich Cardo, José; Duato Marín, José Francisco (Springer Verlag (Germany), 2011-06)
    Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the ...
  • Icon
    Cost-efficient on-chip routing implementations for CMP and MPSoC systems 
    Rodrigo Mocholí, Samuel; Flich Cardo, José; Roca Pérez, Antoni; Medardoni, Simone; Bertozzi, Davide; Camacho Villanueva, Jesús; Silla Jiménez, Federico; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2011-04)
    [EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while ...
  • thumb
    CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs 
    Zoni, Davide; Flich Cardo, José; Fornaciari, William (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    [EN] Router's buffer design and management strongly influence energy, area and performance of on-chip networks, hence it is crucial to encompass all of these aspects in the design process. At the same time, the NoC design ...
  • thumb
    Design, implementation, and analysis of router architectures and network topologies for FPGA-Based Multicore System 
    Juvaa, Boldbaatar (Universitat Politècnica de València, 2015-09-29)
    [EN] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads ...
  • thumb
    Efficient routing in heterogeneous SoC designs with small implementation overhead 
    Cano Reyes, José; Flich Cardo, José; Roca Pérez, Antoni; Duato Marín, José Francisco; Coppola, Marcello; Locatelli, Riccardo (Institute of Electrical and Electronics Engineers (IEEE), 2014-03)
    In application-specific SoCs, the irregularity of the topology ends up in a complex and customized implementation of the routing algorithm, usually relying on routing tables implemented with memory structures at source end ...
  • thumb
    HoL-blocking avoidance in NoCs 
    Escamilla López, José Vicente (Universitat Politècnica de València, 2013-06-18)
    [ES] Se presentan dos mecanismos para eliminar el "head-of-line blocking" en el contexto de las redes en chip. Una de los mecanismos está orientado a la eliminación del HoL-blocking mediante la detección de ráfagas de ...
  • Icon
    On the impact of within-die process variation in GALS-Based NoC Performance 
    Hernández Luz, Carles; Roca Pérez, Antoni; Silla Jiménez, Federico; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-02)
    [EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...