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Cache architectures based on heterogeneous technologies to deal with manufacturing errors

Lorente Garcés, Vicente Jesús (Universitat Politècnica de València, 2015-12-02)

[EN] SRAM technology has traditionally been used to implement processor caches since it is the fastest existing RAM technology.However,one of the major drawbacks of this technology is its high energy consumption.To reduce ...
On the impact of within-die process variation in GALS-Based NoC Performance

Hernández Luz, Carles; Roca Pérez, Antoni; Silla Jiménez, Federico; Flich Cardo, José; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2012-02)

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...
Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Strano, Alessandro; Hernández Luz, Carles; Silla Jiménez, Federico; Bertozzzi, Davide (IGI Global, 2011)

[EN] Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and ...

Mostrando ítems 1-3 de 3