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Mostrando ítems 1-3 de 3

Análisis y evaluación de prestaciones del empleo de técnicas de caché para acelerar el proceso de búsqueda en tablas de páginas

Ramis Fuambuena, Alberto (Universitat Politècnica de València, 2015-10-29)

[EN] The process of translate virtual adresses to physical addresses made by the processor's MMU requires multiple memory acceses to retrieve the input of each of the levels of the tree in the page table structure. The ...
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

Esteve García, Albert (Universitat Politècnica de València, 2017-09-01)

Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects ...
TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction

Esteve Garcia, Albert; Ros Bardisa, Alberto; Robles Martínez, Antonio; Gómez Requena, María Engracia (Institute of Electrical and Electronics Engineers, 2018)

[EN] Discerning the private or shared condition of the data accessed by the applications is an increasingly decisive approach to achieving efficiency and scalability in multi- and many-core systems. Since most memory ...

Mostrando ítems 1-3 de 3