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Listar por palabra clave "VLSI"

Mostrando ítems 1-11 de 11

Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes

García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Springer Verlag (Germany), 2013-04)

A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modifed to avoid ...
Development of an Automated RTL to GDSII Flow for ASIC Design using Cadence Commercial Tools

Moros Badenes, Jordi (Universitat Politècnica de València, 2024-10-10)

[ES] En este Trabajo de Fin de Máster se propone el desarrollo de un flujo de trabajo automatizado y adaptable para la implementación de ASIC, con el que facilitar el proceso de transformar un diseño en un chip fabricable. ...
Diseño de decodificadores de altas prestaciones para código LDPC

Angarita Preciado, Fabián Enrique (Universitat Politècnica de València, 2013-09-02)

En esta tesis se han investigado los algoritmos de decodificación para códigos de comprobación de paridad de baja densidad (LDPC) y las arquitecturas para la implementación hardware de éstos. El trabajo realizado se centra ...
Diseño e implementación en FPGA de decodificadores de códigos Reed-Solomon para operar a Gbps

Perrone, Gabriele (Universitat Politècnica de València, 2016-11-25)

[EN] Reed-Solomon error correcting codes are being included in the last 100 Gbps Ethernet standards. The aim of this work is the design and implementation of hardware architectures suitable for decoding Reed-Solomon codes ...
Implementación VLSI del algoritmo de proyecciones sucesivas para detección de sistemas MIMO

Marín-Roig Ramón, José (Universitat Politècnica de València, 2016-04-05)

[EN] The insatiable demand for bandwidth of communication on the part of end-users, linked to the lowering the price of the terminals and in telecommunication services have led to a spectacular growth of the wireless ...
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes

Angarita Preciado, Fabián Enrique; Sansaloni Balaguer, Trinidad Mª; Canet Subiela, Mª José; Valls Coquillat, Javier (Springer Verlag (Germany), 2012-02)

This paper presents an architecture for high-throughput decoding of high-rate Low-Density Parity-Check (LDPC) codes. The proposed architecture is a modification of the sliced message passing (SMP) decoding architecture ...
Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation

Angarita Preciado, Fabián Enrique; Marín-Roig Ramón, José; Almenar Terré, Vicenç; Valls Coquillat, Javier (Institution of Engineering and Technology (IET), 2012-11-06)

This study proposes a new low-complexity decoding algorithm for low-density parity check codes, which is a variation of the offset min-sum algorithm and achieves a similar performance with lower hardware cost. A finite ...
Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes

Angarita, Fabián; Sansaloni Balaguer, Trinidad Mª; Pérez Pascual, Mª Asunción; Valls Coquillat, Javier (Springer Verlag (Germany), 2012-08)

Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated ...
Power Analysis and Optimization of an ASIC IP for the new wideband wireless communications, Wi-Fi 7 (IEEE 802.11be)

Moros Badenes, Jordi (Universitat Politècnica de València, 2022-10-04)

[ES] En aquest projecte, l'alumne realitzarà una anàlisi del consum d'energia d'una de les nostres IP de Wi-Fi amb eines comercials. Estudiarà els diferents fluxos disponibles per a anàlisi de potència i estimació de ...
Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor

Angarita, Fabián; Valls Coquillat, Javier; Almenar Terré, Vicenç; Torres Carot, Vicente (Institute of Electrical and Electronics Engineers (IEEE), 2014-07)

This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum ...
VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz Jucht, Jesús Omar (Universitat Politècnica de València, 2016-11-04)

[EN] This thesis studies the design of low-complexity soft-decision Non-Binary Low-Density Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at ...

Mostrando ítems 1-11 de 11

Listar por palabra clave "VLSI"

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