- -

Listar por palabra clave "VLSI design"

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Listar por palabra clave "VLSI design"

Ordenar por:Orden:Resultados:

  • thumb
    High-Performance NB-LDPC Decoder With Reduction of Message Exchange 
    Lacruz, Jesus O.; García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016-05)
    This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node ...
  • thumb
    One minimum only trellis decoder for non-binary low-density parity-check codes 
    Lacruz, Jesús Omar; García Herrero, Francisco Miguel; Valls Coquillat, Javier; Declercq, David (Institute of Electrical and Electronics Engineers (IEEE), 2015-01)
    A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, ...
  • thumb
    Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm 
    Lacruz, Jesús O.; García Herrero, Francisco Miguel; Canet Subiela, Mª José; Valls Coquillat, Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016-02-04)
    Non-binary LDPC codes outperform its binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node processor, for high-order Galois fields higher ...