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Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems

Martí-Campoy, Antonio; Rodríguez-Ballester, Francisco (IEEE, 2019-09-13)

[EN] Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the ...
LUT saving in embedded FPGAs for cache locking in real-time systems

Martí Campoy, Antonio; Rodríguez Ballester, Francisco; Ors Carot, Rafael (2013)

[EN] In recent years, cache locking have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular ...
Using dynamic, full cache locking and genetic algorithms for cache size minimization in multitasking, preemptive, real-time systems

Martí Campoy, Antonio; Rodríguez Ballester, Francisco; Ors Carot, Rafael (Springer Verlag (Germany), 2013)

Cache locking have shown during the last years their usefulness easing the schedulability analysis of multitasking, preemptive, real-time systems. Cache locking provides a high degree of predictability while system performance ...

Mostrando ítems 1-3 de 3