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Cache-Hierarchy contention-aware scheduling in CMPs

Feliu Pérez, Josué; Petit Martí, Salvador Vicente; Sahuquillo Borrás, Julio; Duato Marín, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2014-03)

To improve chip multiprocessor (CMP) performance, recent research has focused on scheduling strategies to mitigate main memory bandwidth contention. Nowadays, commercial CMPs implement multilevel cache hierarchies that are ...
Coordinate Channel-Aware Page Mapping Policy and Memory Scheduling for Reducing Memory Interference Among Multimedia Applications

Jia, Gangyong; Han, Guangjie; Li, Aohan; Lloret, Jaime (Institute of Electrical and Electronics Engineers, 2017-12)

[EN] In a modern multicore system, memory is shared among more and more concurrently running multimedia applications. Therefore, memory contention and interference are more andmore serious, inducing system performance ...
Hardware resources contention-aware scheduling of hard real-time multiprocessor systems

Aceituno-Peinado, José María; Guasque Ortega, Ana; Balbastre, Patricia; Simó Ten, José Enrique; Crespo, Alfons (Elsevier, 2021-09)

[EN] In hard real-time embedded systems, switching to multicores is a step that most application domains delay asmuch as possible. This is mainly due to the number of sources of indeterminism, which mainly involve ...

Mostrando ítems 1-3 de 3