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Listar por palabra clave "Network-on-chip"

Mostrando ítems 1-10 de 10

A low-latency modular switch for CMP systems

Roca Pérez, Antoni; Flich Cardo, José; Silla Jiménez, Federico; Duato Marín, José Francisco (Elsevier, 2011-11)

[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we ...
Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, Carles (Universitat Politècnica de València, 2012-07-19)
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca Pérez, Antoni; Hernández Luz, Carles; Lodde, Mario; Flich Cardo, José (Elsevier, 2015-07)

Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...
Built-in fast gather control network for efficient support of coherence protocols

Lodde, Mario; Roca Pérez, Antoni; Flich Cardo, José (Institution of Engineering and Technology (IET), 2013-03)

[EN] Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data ...
Conflict-Free Networks on Chip for Real Time Systems

Picornell Sanjuan, Tomás (Universitat Politècnica de València, 2021-11-22)

[ES] La constante necesidad de un mayor rendimiento para cumplir con la gran demanda de potencia de cómputo de las nuevas aplicaciones, (ej. sistemas de conducción autónoma), obliga a la industria a apostar por la tecnología ...
Efficient built-in NoC support for gather operations in invalidation-based coherence protocols

Lodde, Mario (Universitat Politècnica de València, 2014-11-28)

[EN] A dedicated control network is used to transmit acknowledgement messages generated by the coherence protocol, thus reducing the traffic in the regular NoC and improving the overall system performance
Runtime home mapping for effective memory resource usage

Lodde, Mario; Flich Cardo, José (Elsevier, 2014-06)

In tiled Chip Multiprocessors (CMPs) last-level cache (LLC) banks are usually shared but distributed among the tiles. A static mapping of cache blocks to the LLC banks leads to poor efficiency since a block may be mapped ...
Savior: A Reliable Fault Resilient Router Architecture for Network-on-Chip

Hussain, Ayaz; Irfan, Muhammad; Baloch, Naveed Khan; Draz, Umar; Ali, Tariq; Glowacz, Adam; Dunai, Larisa; Antonino Daviu, José Alfonso (MDPI AG, 2020-11)

[EN] The router plays an important role in communication among different processing cores in on-chip networks. Technology scaling on one hand has enabled the designers to integrate multiple processing components on a single ...
Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

Lodde, Mario (Universitat Politècnica de València, 2014-02-04)

La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo ...
Virtualizing network-on-chip resources in chip-multiprocessors

Triviño, Francisco; Sánchez, José L.; Alfaro, Francisco J.; Flich Cardo, José (Elsevier, 2011-03)

[EN] The number of cores on a single silicon chip is rapidly growing and chips containing tens or even hundreds of identical cores are expected in the future. To take advantage of multicore chips, multiple applications ...