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Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications

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Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications

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dc.contributor.author Pons-Escat, Lucía es_ES
dc.contributor.author Selfa, Vicent es_ES
dc.contributor.author Sahuquillo Borrás, Julio es_ES
dc.contributor.author Petit Martí, Salvador Vicente es_ES
dc.contributor.author Pons Terol, Julio es_ES
dc.date.accessioned 2023-12-22T07:14:16Z
dc.date.available 2023-12-22T07:14:16Z
dc.date.issued 2018-08-31 es_ES
dc.identifier.isbn 978-3-319-96983-1 es_ES
dc.identifier.issn 0302-9743 es_ES
dc.identifier.uri http://hdl.handle.net/10251/201063
dc.description.abstract [EN] Resource sharing is a major concern in current multicore processors. Among the shared system resources, the Last Level Cache (LLC) is one of the most critical, since destructive interference between applications accessing it implies more off-chip accesses to main memory, which incur long latencies that can severely impact the overall system performance. To help alleviate this issue, current processors implement huge LLCs, but even so, inter-application interference can harm the performance of a subset of the running applications when executing multiprogram workloads. For this reason, recent Intel processors feature Cache Allocation Technologies (CAT) to partition the cache and assign subsets of cache ways to groups of applications. This paper proposes the Critical-Aware (CA) LLC partitioning approach, which leverages CAT and improves the performance of multiprogram workloads, by identifying and protecting the applications whose performance is more damaged by LLC sharing. Experimental results show that CA improves turnaround time on average by 15%, and up to 40% compared to a baseline system without partitioning. es_ES
dc.description.sponsorship This work was supported by the Spanish Ministerio de Economia y Competitividad (MINECO) and Plan E funds, under grants TIN2015-66972-C5-1-R and TIN2017-92139-EXP. It was also supported by the ExaNest project, with funds from the European Union Horizon 2020 project, with grant agreement No 671553. es_ES
dc.language Inglés es_ES
dc.publisher Springer es_ES
dc.relation.ispartof Euro-Par 2018: Parallel Processing es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Multicore cache es_ES
dc.subject Multicore architectures es_ES
dc.subject Intel es_ES
dc.subject Cache partitioning es_ES
dc.subject Cache allocation technologies es_ES
dc.subject Cache director technologies es_ES
dc.subject Cache interference es_ES
dc.subject Shared caches es_ES
dc.subject Performance es_ES
dc.subject Application clustering es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications es_ES
dc.type Comunicación en congreso es_ES
dc.type Artículo es_ES
dc.type Capítulo de libro es_ES
dc.identifier.doi 10.1007/978-3-319-96983-1_43 es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/671553/EU es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2017-92139-EXP/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TIN2015-66972-C5-1-R/ES/TECNICAS PARA LA MEJORA DE LAS PRESTACIONES, COSTE Y CONSUMO DE ENERGIA DE LOS SERVIDORES/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Pons-Escat, L.; Selfa, V.; Sahuquillo Borrás, J.; Petit Martí, SV.; Pons Terol, J. (2018). Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications. Springer. 603-615. https://doi.org/10.1007/978-3-319-96983-1_43 es_ES
dc.description.accrualMethod S es_ES
dc.relation.conferencename 24th International European Conference on Parallel and Distributed Computing (Euro-Par 2018) es_ES
dc.relation.conferencedate Agosto 27-31,2018 es_ES
dc.relation.conferenceplace Turin, Italy es_ES
dc.relation.publisherversion https://doi.org/10.1007/978-3-319-96983-1_43 es_ES
dc.description.upvformatpinicio 603 es_ES
dc.description.upvformatpfin 615 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.relation.pasarela S\369355 es_ES
dc.contributor.funder MINISTERIO DE ECONOMIA Y EMPRESA es_ES
dc.contributor.funder COMISION DE LAS COMUNIDADES EUROPEA es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
dc.description.references Sodani, A., et al.: Knights landing: second-generation intel xeon phi product. IEEE Micro 36(2), 34–46 (2016) es_ES
dc.description.references Qureshi, M.K., Patt, Y.N.: Utility-based cache partitioning: a low-overhead, high-performance, runtime mechanism to partition shared caches. In: Proceedings of MICRO, pp. 423–432 (2006) es_ES
dc.description.references Manikantan, R., Rajan, K., Govindarajan, R.: Probabilistic shared cache management (PriSM). In: Proceedings of the 39th Annual International Symposium on Computer Architecture (ISCA), pp. 428–439 (2012) es_ES
dc.description.references El-Sayed, N., Mukkara, A., Tsai, P.A., Kasture, H., Ma, X., Sanchez, D.: Kpart: a hybrid cache partitioning-sharing technique for commodity multicores. In: Proceedings of HPCA (2018) es_ES
dc.description.references Selfa, V., Sahuquillo, J., Eeckhout, L., Petit, S., Gómez, M.E.: Application clustering policies to address system fairness with intel’s cache allocation technology. In: Proceedings of PACT, pp. 194–205 (2017) es_ES
dc.description.references Feliu, J., Sahuquillo, J., Petit, S., Duato, J.: Addressing fairness in SMT multicores with a progress-aware scheduler. In: Proceedings of IPDPS, pp. 187–196 (2015) es_ES
dc.description.references Van Craeynest, K., Akram, S., Heirman, W., Jaleel, A., Eeckhout, L.: Fairness-aware scheduling on single-ISA heterogeneous multi-cores. In: Proceedings of PACT, pp. 177–188 (2013) es_ES
dc.description.references Wu, C., Li, J., Xu, D., Yew, P.C., Li, J., Wang, Z.: FPS: a fair-progress process scheduling policy on shared-memory multiprocessors. J. Trans. Parallel Distrib. Syst. 26(2), 444–454 (2015) es_ES
dc.description.references Eyerman, S., Eeckhout, L.: System-level performance metrics for multiprogram workloads. IEEE Micro 28(3), 42–53 (2008) es_ES
dc.description.references Henning, J.L.: SPEC CPU2006 benchmark descriptions. Comput. Archit. News 34(4), 1–17 (2006) es_ES
dc.description.references Miller, J.: Short report: reaction time analysis with outlier exclusion: bias varies with sample size. J. Exp. Psychol. 43(4), 907–912 (1991) es_ES
dc.description.references Leys, C., Ley, C., Klein, O., Bernard, P., Licata, L.: Detecting outliers: do not use standard deviation around the mean, use absolute deviation around the median. J. Exp. Soc. Psychol. 49(4), 764–766 (2013) es_ES
dc.description.references Gleixner, T., Molnar, I.: Performance counters for Linux (2009) es_ES
dc.description.references Van Craeynest, K., Akram, S., Heirman, W., Jaleel, A., Eeckhout, L.: Fairness-aware scheduling on single-ISA heterogeneous multi-cores. In: Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques. PACT 2013, Piscataway, NJ, USA, pp. 177–188. IEEE Press (2013) es_ES
dc.description.references Lo, D., Cheng, L., Govindaraju, R., Ranganathan, P., Kozyrakis, C.: Heracles: improving resource efficiency at scale. In: Proceedings of ISCA, pp. 450–462 (2015) es_ES
dc.description.references Zhu, H., Erez, M.: Dirigent: enforcing QoS for latency-critical tasks on shared multicore systems. In: Proceedings of ASPLOS, pp. 33–47 (2016) es_ES
dc.description.references Funaro, L., Ben-Yehuda, O.A., Schuster, A.: Ginseng: market-driven LLC allocation. In: Proceedings of USENIX, pp. 295–308 (2016) es_ES
dc.description.references Subramanian, L., Seshadri, V., Ghosh, A., Khan, S., Mutlu, O.: The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory. In: Proceedings of MICRO, pp. 62–75 (2015) es_ES
dc.description.references Sanchez, D., Kozyrakis, C.: Vantage: scalable and efficient fine-grain cache partitioning. In: Proceedings of ISCA, pp. 57–68 (2011) es_ES
dc.description.references Sahuquillo, J., Pont, A.: The filter cache: a run-time cache management approach1. In: 25th EUROMICRO 1999 Conference (1999) es_ES


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