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High speed RS(255, 239) decoder based on LCC decoding

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High speed RS(255, 239) decoder based on LCC decoding

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dc.contributor.author García Herrero, Francisco Miguel es_ES
dc.contributor.author Valls Coquillat, Javier es_ES
dc.contributor.author Meher, P. K. es_ES
dc.date.accessioned 2015-02-09T09:20:22Z
dc.date.available 2015-02-09T09:20:22Z
dc.date.issued 2011-12
dc.identifier.issn 0278-081X
dc.identifier.uri http://hdl.handle.net/10251/46831
dc.description.abstract Algebraic Soft-Decision Decoding (ASD) of Reed-Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, the Low Complexity Chase (LCC) decoding is the one with the lowest implementation cost. LCC decoding is based on generating 2 ¿ test vectors, where ¿ symbols are selected as the least reliable symbols for which hard-decision or the second more reliable decision are employed. Previous decoding algorithms for LCC decoders are based on interpolation and re-encoding techniques. On the other hand, HDD algorithms such as the Berlekamp-Massey (BM) algorithm or the Euclidean algorithm, despite of their low computational complexity, are not considered suitable for LCC decoding. In this paper, we present a new approach to LCC decoding based on one of these HDD algorithms, the inversion-less Berlekamp-Massey (iBM) algorithm, where the test vectors are selected for correction during decoding on occurrence of hard-decision decoding failure. The proposed architecture when applied to a RS(255, 239) code with ¿=3, saves a 20.5% and 2% of area compared to the LCC with factorization and a factorization-free decoder, respectively. In both cases, the latency is reduced by 34.5%, which is an increase of throughput rate in the same percentage since the critical path is the same in all the competing architectures. So an efficiency of at least 56% in terms of area-delay product can be obtained, compared with previous works. A complete RS(255, 239) LCC decoder with ¿=3 has been coded in VHDL and synthesized for implementation in Vitex-5 FPGA device, and by using SAED 90 nm standard cell library as well, and find a decoding rate of 710 Mbps and 4.2 Gbps and area of 2527 slices and 0.36 mm 2, respectively. © 2011 Springer Science+Business Media, LLC. es_ES
dc.description.sponsorship This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787. en_EN
dc.language Español es_ES
dc.publisher Springer Verlag (Germany) es_ES
dc.relation.ispartof Circuits, Systems, and Signal Processing es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject ASIC implementation es_ES
dc.subject FPGA implementation es_ES
dc.subject Low complexity chase decoder es_ES
dc.subject Reed-Solomon es_ES
dc.subject Soft-decision es_ES
dc.subject Algebraic soft-decision decoding es_ES
dc.subject Coding gains es_ES
dc.subject Critical Paths es_ES
dc.subject Decoding algorithm es_ES
dc.subject Decoding failure es_ES
dc.subject Decoding rates es_ES
dc.subject Euclidean algorithms es_ES
dc.subject FPGA devices es_ES
dc.subject High-speed es_ES
dc.subject Implementation cost es_ES
dc.subject Low complexity es_ES
dc.subject Proposed architectures es_ES
dc.subject Re-encoding es_ES
dc.subject Reed solomon es_ES
dc.subject Reliable decision es_ES
dc.subject Standard cell es_ES
dc.subject Test vectors es_ES
dc.subject Throughput rate es_ES
dc.subject Algorithms es_ES
dc.subject Computational complexity es_ES
dc.subject Electric batteries es_ES
dc.subject Factorization es_ES
dc.subject Decoding es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title High speed RS(255, 239) decoder based on LCC decoding es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1007/s00034-011-9327-4
dc.relation.projectID info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/ es_ES
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.description.bibliographicCitation García Herrero, FM.; Valls Coquillat, J.; Meher, PK. (2011). High speed RS(255, 239) decoder based on LCC decoding. Circuits, Systems, and Signal Processing. 30(6):1643-1669. https://doi.org/10.1007/s00034-011-9327-4 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1007/s00034-011-9327-4 es_ES
dc.description.upvformatpinicio 1643 es_ES
dc.description.upvformatpfin 1669 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 30 es_ES
dc.description.issue 6 es_ES
dc.relation.senia 210720
dc.contributor.funder Ministerio de Ciencia e Innovación es_ES
dc.contributor.funder European Regional Development Fund es_ES
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