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dc.contributor.author | Petit Martí, Salvador Vicente | es_ES |
dc.contributor.author | Ubal Tena, Rafael | es_ES |
dc.contributor.author | Sahuquillo Borrás, Julio | es_ES |
dc.contributor.author | López Rodríguez, Pedro Juan | es_ES |
dc.date.accessioned | 2015-05-06T16:58:16Z | |
dc.date.available | 2015-05-06T16:58:16Z | |
dc.date.issued | 2014-07 | |
dc.identifier.issn | 1063-8210 | |
dc.identifier.uri | http://hdl.handle.net/10251/49811 | |
dc.description | © © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.” | es_ES |
dc.description.abstract | Modern superscalar processors implement register renaming using either random access memory (RAM) or content-addressable memories (CAM) tables. The design of these structures should address both access time and misprediction recovery penalty. Although direct-mapped RAMs provide faster access times, CAMs are more appropriate to avoid recovery penalties. The presence of associative ports in CAMs, however, prevents them from scaling with the number of physical registers and pipeline width, negatively impacting performance, area, and energy consumption at the rename stage. In this paper, we present a new hybrid RAM CAM register renaming scheme, which combines the best of both approaches. In a steady state, a RAM provides fast and energy-efficient access to register mappings. On misspeculation, a low-complexity CAM enables immediate recovery. Experimental results show that in a four-way state-ofthe- art superscalar processor, the new approach provides almost the same performance as an ideal CAM-based renaming scheme, while dissipating only between 17% and 26% of the original energy and, in some cases, consuming less energy than purely RAM-based renaming schemes. Overall, the silicon area required to implement the hybrid RAM CAM scheme does not exceed the area required by conventional renaming mechanisms. | es_ES |
dc.description.sponsorship | This work was supported in part by the Spanish MINECO under Grant TIN2012-38341-C04-01. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es_ES |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Content-addressable memory (CAM) complexity | es_ES |
dc.subject | Energy consumption | es_ES |
dc.subject | Energy efficiency | es_ES |
dc.subject | Misspeculation recovery | es_ES |
dc.subject | Register renaming. | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Efficient register renaming and recovery for high-performance processors | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/TVLSI.2013.2270001 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2012-38341-C04-01/ES/MEJORA DE LA ARQUITECTURA DE SERVIDORES, SERVICIOS Y APLICACIONES/ | |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Petit Martí, SV.; Ubal Tena, R.; Sahuquillo Borrás, J.; López Rodríguez, PJ. (2014). Efficient register renaming and recovery for high-performance processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22(7):1506-1514. https://doi.org/10.1109/TVLSI.2013.2270001 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TVLSI.2013.2270001 | es_ES |
dc.description.upvformatpinicio | 1506 | es_ES |
dc.description.upvformatpfin | 1514 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 22 | es_ES |
dc.description.issue | 7 | es_ES |
dc.relation.senia | 280070 | |
dc.contributor.funder | Ministerio de Economía y Competitividad |